/**
  @file drv_acc.c

  @date 2010-02-26

  @version v5.1

  The file implement driver acc IOCTL defines and macros
*/

#include "sal.h"
#include "drv_api.h"
#include "usw/include/drv_app.h"
#include "usw/include/drv_ftm.h"
#include "usw/include/drv_common.h"
#include "usw/include/drv_error.h"
#include "usw/include/drv_enum.h"
#include "usw/include/drv_sdb.h"
#include "usw/include/drv_io.h"
#include "dal.h"
/**********************************************************************************
              Define Gloabal var, Typedef, define and Data Structure
***********************************************************************************/
#define IPFIX_AT_COMBINE_SIZE 67
#define IPFIX_TMM_COMBINE_SIZE 60

typedef uint32 ds_t[64];
extern uint8 drv_vchip_pp_base[DRV_MAX_CHIP_NUM];
#if defined(EMULATION_ENV) && !defined(EMULATOR_ENV)
uint8 g_drv_lchip_2_pp[8] = {0, 1, 2, 3, 0, 1, 2, 3};
uint8 g_drv_lchip_2_core[8] = {0, 0, 0, 0, 1, 1, 1, 1};
#endif
enum hash_module_e
{
    HASH_MODULE_EGRESS_SCL0,
    HASH_MODULE_EGRESS_SCL1,
    HASH_MODULE_RMEP,
    HASH_MODULE_FIB_HOST0,
    HASH_MODULE_FIB_HOST1,
    HASH_MODULE_FLOW,
    #if 0
    HASH_MODULE_GEMPORT,
    #endif
    HASH_MODULE_INGRESS_IPFIX,
    HASH_MODULE_EGRESS_IPFIX,
    HASH_MODULE_MPLS,
    HASH_MODULE_OAM,
    #if 0
    HASH_MODULE_QUEUEMAP,
    #endif
    HASH_MODULE_USERID,
    HASH_MODULE_USERID1,
    HASH_MODULE_XLOOKUP0,
    HASH_MODULE_XLOOKUP1,
    HASH_MODULE_XSEC_RX,
    HASH_MODULE_XSEC_TX,
    HASH_MODULE_NUM,
};

typedef enum hash_module_e hash_module_t;

enum drv_ipfix_acc_req_type_e
{
    DRV_IPFIX_REQ_WRITE_BY_IDX,
    DRV_IPFIX_REQ_WRITE_BY_KEY,
    DRV_IPFIX_REQ_LKP_BY_KEY,
    DRV_IPFIX_REQ_LKP_BY_IDX
};
typedef enum drv_ipfix_acc_req_type_e drv_ipfix_acc_req_type_t;

struct key_lookup_result_s
{
   uint32 bucket_index;
};
typedef struct key_lookup_result_s key_lookup_result_t;

struct key_lookup_info_s
{
    uint8* key_data;
    uint32 key_bits;
    uint32 polynomial;
    uint32 poly_len;
    uint32 type;
    uint32 crc_bits;
};
typedef struct key_lookup_info_s key_lookup_info_t;

typedef struct drv_hash_param_s
{
   uint8 cam_step;
   uint8 cam_num;
   uint32 cam_tbl_id;
}drv_hash_param_t;


typedef struct drv_acc_master_s
{
    drv_hash_param_t    hash_info[DRV_ACC_HASH_MODULE_NUM];
}drv_acc_master_t;

drv_acc_master_t   g_drv_app_master[DRV_MAX_CHIP_NUM];


#define FIB_ACC_LOCK(lchip)    \
  if(p_drv_master[lchip]->fib_acc_mutex) {sal_mutex_lock(p_drv_master[lchip]->fib_acc_mutex);}
#define FIB_ACC_UNLOCK(lchip)  \
  if(p_drv_master[lchip]->fib_acc_mutex) {sal_mutex_unlock(p_drv_master[lchip]->fib_acc_mutex);}
#define CPU_ACC_LOCK(lchip)    \
  if(p_drv_master[lchip]->cpu_acc_mutex) {sal_mutex_lock(p_drv_master[lchip]->cpu_acc_mutex);}
#define CPU_ACC_UNLOCK(lchip)  \
  if(p_drv_master[lchip]->cpu_acc_mutex) {sal_mutex_unlock(p_drv_master[lchip]->cpu_acc_mutex);}
#define IPFIX_ACC_LOCK(lchip)  \
  if(p_drv_master[lchip]->ipfix_acc_mutex) {sal_mutex_lock(p_drv_master[lchip]->ipfix_acc_mutex);}
#define IPFIX_ACC_UNLOCK(lchip)\
  if(p_drv_master[lchip]->ipfix_acc_mutex) {sal_mutex_unlock(p_drv_master[lchip]->ipfix_acc_mutex);}
#define CID_ACC_UNLOCK(lchip)\
  if(p_drv_master[lchip]->cid_acc_mutex) {sal_mutex_unlock(p_drv_master[lchip]->cid_acc_mutex);}
#define CID_ACC_LOCK(lchip)  \
  if(p_drv_master[lchip]->cid_acc_mutex) {sal_mutex_lock(p_drv_master[lchip]->cid_acc_mutex);}

#define MPLS_ACC_LOCK(lchip)  \
  if(p_drv_master[lchip]->mpls_acc_mutex) {sal_mutex_lock(p_drv_master[lchip]->mpls_acc_mutex);}
#define MPLS_ACC_UNLOCK(lchip)  \
  if(p_drv_master[lchip]->mpls_acc_mutex) {sal_mutex_unlock(p_drv_master[lchip]->mpls_acc_mutex);}

#define GEMPORT_ACC_LOCK(lchip)  \
  if(p_drv_master[lchip]->gemport_acc_mutex) {sal_mutex_lock(p_drv_master[lchip]->gemport_acc_mutex);}
#define GEMPORT_ACC_UNLOCK(lchip)  \
  if(p_drv_master[lchip]->gemport_acc_mutex) {sal_mutex_unlock(p_drv_master[lchip]->gemport_acc_mutex);}


#define DRV_ACC_GET_SLICE_ID(slice_bmp, slice_id)   \
    do{\
        switch(slice_bmp)\
        {\
            case 0x2: \
                {slice_id = 1; break;}\
            case 0x4: \
                {slice_id = 2; break;}\
            case 0x8: \
                {slice_id = 3; break;}\
            case 0x0:\
            case 0x1:\
            case 0xF:\
                {slice_id = 0; break;}\
            default:\
                return DRV_E_INVALID_PARAMETER;\
        }\
    }while(0)

extern int32
drv_model_hash_combined_key(uint8* dest_key, uint8* src_key, uint32 len, uint32 tbl_id);
extern int32
drv_model_hash_mask_key(uint8* dest_key, uint8* src_key, hash_module_t hash_module, uint32 key_type);
extern int32
drv_model_hash_un_combined_key(uint8* dest_key, uint8* src_key, uint32 len, uint32 tbl_id);
#if defined(TSINGMA_MX) || defined(TSINGMA_GX) || defined(ARCTIC)
 int32
drv_model_hash_combined_key(uint8* dest_key, uint8* src_key, uint32 len, uint32 tbl_id)
{
return 0;
}

 int32
drv_model_hash_mask_key(uint8* dest_key, uint8* src_key, hash_module_t hash_module, uint32 key_type)
{
return 0;
}

int32
drv_model_hash_un_combined_key(uint8* dest_key, uint8* src_key, uint32 len, uint32 tbl_id)
{
return 0;
}
#endif

int32
drv_usw_acc_host0_prepare(uint8 lchip, drv_acc_in_t* acc_in, uint32* req);
int32
drv_usw_acc_host0_process(uint8 lchip, uint32* i_cpu_req, uint32* o_cpu_rlt,uint8 sleep_en, uint8 oper_bmp);
int32
drv_usw_acc_host0(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

int32
drv_usw_acc_host0_result(uint8 lchip, drv_acc_in_t* acc_in, uint32* fib_acc_cpu_rlt, drv_acc_out_t* out);

extern int32
drv_usw_chip_reg_read(uint8 lchip, uint32 tbl_id, uint32 index, uint8 oper_bmp, uint32* data);
extern int32
drv_usw_chip_reg_write(uint8 lchip, uint32 tbl_id, uint32 index, uint8 oper_bmp, uint32* data);

uint32
drv_hash_crc(uint32 seed, uint8 *data, uint32 bit_len, uint32 poly, uint32 poly_len)
{
    uint32 crc = 0;
    int32 i = 0;
    uint32 msb_bit = 0;
    uint32 poly_mask = 0;
    uint32 topone=0;
    poly_mask = (1<<poly_len) -1;
    topone = (1 << (poly_len-1));
    crc = seed & poly_mask;

    for (i = (bit_len-1); i >=0; i--) {  /* bits*/
      msb_bit = ((data[i>>3]>>(i&0x7))&0x1) << (poly_len-1);
      crc ^= msb_bit;
      crc = (crc << 1) ^ ((crc & topone) ? poly: 0);
       /*bit_len --;*/
    }

    crc &= poly_mask;
    return crc;
}

uint16
drv_hash_xor16(uint16* data, uint32 bit_len)
{
    uint32 i = 0;
    uint16 result = 0;
    uint16 len = bit_len>>4;
    uint16 last_bits = bit_len&0xF;

    for (i = 0; i < len; i++)
    {
        result ^= data[i];
    }

    if (last_bits)
    {
        result ^= (data[len]&((1<<last_bits)-1));
    }

    return result;
}

int32
drv_usw_get_cam_info(uint8 lchip, uint8 hash_module, uint32* tbl_id, uint8* num)
{
    if (hash_module == DRV_ACC_HASH_MODULE_FIB_HOST1)
    {
        *tbl_id = DsFibHost1HashCam_t;
        *num = DRV_CONST(DRV_FIB_HOST1_CAM_NUM);
    }
     else if (hash_module == DRV_ACC_HASH_MODULE_OAM)
    {
        *tbl_id =  DsOamHashCam_t ;
        *num = DRV_CONST(DRV_OAM_HASH_CAM_NUM);
    }
     else if (hash_module == DRV_ACC_HASH_MODULE_RMEP)
    {
        *tbl_id =  DsEthOamRmepHashCam_t ;
        *num = DRV_CONST(DRV_RMEP_HASH_CAM_NUM);
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_EGRESS_XC)
    {
        *tbl_id = DsEgressXcOamHashCam_t;
        *num = DRV_CONST(DRV_XC_OAM_HASH_CAM_NUM);
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_EGRESS_SCL || hash_module == DRV_ACC_HASH_MODULE_X_FLOW)
    {
        *tbl_id = 0;
        *num = 0;       /**************/
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_FLOW)
    {
        *tbl_id = DsFlowHashCam_t;
        *num = DRV_CONST(DRV_FLOW_HASH_CAM_NUM);
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_USERID)
    {
        *tbl_id = DsUserIdHashCam_t;
        if (DRV_IS_DUET2(lchip))
        {
            *num = DRV_CONST(DRV_USER_ID_HASH_CAM_NUM);
        }
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_FIB_HOST0)
    {
        *tbl_id = (DRV_IS_DUET2(lchip)) ? DsFibHost0HashCam_t : DsFibHost0HashIpCam_t;
        *num = DRV_CONST(DRV_FIB_HOST0_CAM_NUM);
    }
    else if(hash_module == DRV_ACC_HASH_MODULE_FDB || hash_module ==DRV_ACC_HASH_MODULE_IPL2MC)
    {
        *tbl_id = (DRV_IS_DUET2(lchip)) ? DsFibHost0HashCam_t : DsFibHost0HashMacCam_t;
        *num = DRV_CONST(DRV_FIB_HOST0_CAM_NUM);
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_MPLS_HASH)
    {
        *tbl_id = DsMplsHashCam_t;
        *num = 64;
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_DOT1AE)
    {
        *tbl_id = DsXSecRxHashCam_t;
        *num = DRV_CONST(DRV_DOT1AE_HASH_CAM_NUM);
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_GEMPORT_HASH)
    {
        *tbl_id = DRV_FROM_TMM(lchip) ? DsGemPortHashCam_t : DsGemHashCam_t;
        *num = DRV_CONST(DRV_GEM_PORT_HASH_CAM_NUM);
    }
    else if (hash_module == DRV_ACC_HASH_MODULE_QUEUE_MAP_HASH)
    {
        *tbl_id = DsQueueMapHashCam_t;
        *num = 16;
    }
    else
    {
        return DRV_E_INVAILD_TYPE;
    }

    return DRV_E_NONE;
}

int32
drv_acc_get_hash_module(uint8 lchip, uint32 tbl_id, uint8* p_module)
{
    switch (tbl_id)
    {
    case DsFibHost0MacHashKey_t:
         *p_module = DRV_ACC_HASH_MODULE_FDB;
          break;
    case DsFibHost0FcoeHashKey_t:
    case DsFibHost0Ipv4HashKey_t:
    case DsFibHost0Ipv6McastHashKey_t:
    case DsFibHost0Ipv6UcastHashKey_t:
    case DsFibHost0TrillHashKey_t:
         *p_module = DRV_ACC_HASH_MODULE_FIB_HOST0;
          break;
    case DsFibHost0MacIpv4McastHashKey_t:
    case DsFibHost0MacIpv6McastHashKey_t:
         if(DRV_FROM_TMM(lchip))
         {
            *p_module = DRV_ACC_HASH_MODULE_IPL2MC;
         }
         else
         {
           *p_module = DRV_ACC_HASH_MODULE_FIB_HOST0;
         }
         break;
    case DsFibHost1FcoeRpfHashKey_t:
    case DsFibHost1Ipv4McastHashKey_t:
    case DsFibHost1Ipv4NatDaPortHashKey_t:
    case DsFibHost1Ipv4NatSaPortHashKey_t:
    case DsFibHost1Ipv6McastHashKey_t:
    case DsFibHost1Ipv6NatDaPortHashKey_t:
    case DsFibHost1Ipv6NatSaPortHashKey_t:
    case DsFibHost1MacIpv4McastHashKey_t:
    case DsFibHost1MacIpv6McastHashKey_t:
    case DsFibHost1TrillMcastVlanHashKey_t:
        *p_module = DRV_ACC_HASH_MODULE_FIB_HOST1;
        break;

    case DsEgressXcOamBfdHashKey_t:
    case DsEgressXcOamCvlanCosPortHashKey_t:
    case DsEgressXcOamCvlanPortHashKey_t:
    case DsEgressXcOamDoubleVlanPortHashKey_t:
    case DsEgressXcOamEthHashKey_t:
    case DsEgressXcOamMplsLabelHashKey_t:
    case DsEgressXcOamMplsSectionHashKey_t:
    case DsEgressXcOamPortCrossHashKey_t:
    case DsEgressXcOamPortHashKey_t:
    case DsEgressXcOamPortVlanCrossHashKey_t:
    case DsEgressXcOamRmepHashKey_t:
    case DsEgressXcOamSvlanCosPortHashKey_t:
    case DsEgressXcOamSvlanPortHashKey_t:
    case DsEgressXcOamSvlanPortMacHashKey_t:
    case DsEgressXcOamTunnelPbbHashKey_t:
        *p_module = DRV_ACC_HASH_MODULE_EGRESS_XC;
        break;
    case DsOamEthHashKey_t:
    case DsOamBfdHashKey_t:
    case DsOamMplsLabelHashKey_t:
    case DsOamMplsSectionHashKey_t:
        *p_module =   DRV_ACC_HASH_MODULE_OAM;
        break;
    case DsEthOamRmepRmepHashKey_t:
         *p_module =   DRV_ACC_HASH_MODULE_RMEP;
        break;
    case DsEgressScl0CvlanCosPortHashKey_t:
    case DsEgressScl0CvlanPortHashKey_t:
    case DsEgressScl0DoubleVlanPortHashKey_t:
    case DsEgressScl0PortCrossHashKey_t:
    case DsEgressScl0PortHashKey_t:
    case DsEgressScl0PortVlanCrossHashKey_t:
    case DsEgressScl0SvlanCosPortHashKey_t:
    case DsEgressScl0SvlanPortHashKey_t:
    case DsEgressScl0SvlanPortMacHashKey_t:
    case DsEgressScl0FidDvpGroupHashKey_t:
    case DsEgressScl0MetadataDvpGroupHashKey_t:
    case DsEgressScl0VpPairHashKey_t:
    case DsEgressScl0I2eCidDvpGroupHashKey_t:
    case DsEgressScl1CvlanCosPortHashKey_t:
    case DsEgressScl1CvlanPortHashKey_t:
    case DsEgressScl1DoubleVlanPortHashKey_t:
    case DsEgressScl1PortCrossHashKey_t:
    case DsEgressScl1PortHashKey_t:
    case DsEgressScl1PortVlanCrossHashKey_t:
    case DsEgressScl1SvlanCosPortHashKey_t:
    case DsEgressScl1SvlanPortHashKey_t:
    case DsEgressScl1SvlanPortMacHashKey_t:
    case DsEgressScl1FidDvpGroupHashKey_t:
    case DsEgressScl1MetadataDvpGroupHashKey_t:
    case DsEgressScl1VpPairHashKey_t:
    case DsEgressScl1I2eCidDvpGroupHashKey_t:
    case DsEgressScl1XHashKey_t:  /*xkey*/
    case DsEgressScl0XHashKey_t:  /*xkey*/  
        *p_module = DRV_ACC_HASH_MODULE_EGRESS_SCL;
        break;

    case DsFlowL2HashKey_t:
    case DsFlowL2L3HashKey_t:
    case DsFlowL3Ipv4HashKey_t:
    case DsFlowL3Ipv6HashKey_t:
    case DsFlowL3MplsHashKey_t:
    case DsFlowNshForwardHashKey_t:
    case DsFlowXKeyDoubleHashKey_t:
    case DsFlowXKeyQuadHashKey_t:
        *p_module = DRV_ACC_HASH_MODULE_FLOW;
        break;

    case DsUserIdCapwapMacDaForwardHashKey_t:
    case DsUserIdCapwapStaStatusHashKey_t:
    case DsUserIdCapwapStaStatusMcHashKey_t:
    case DsUserIdCapwapVlanForwardHashKey_t:
    case DsUserIdCvlanCosPortHashKey_t:
    case DsUserIdCvlanPortHashKey_t:
    case DsUserIdDoubleVlanPortHashKey_t:
    case DsUserIdEcidNameSpaceHashKey_t:
    case DsUserIdIngEcidNameSpaceHashKey_t:
    case DsUserIdIpv4PortHashKey_t:
    case DsUserIdIpv4SaHashKey_t:
    case DsUserIdIpv4DaHashKey_t:
    case DsUserIdIpv6PortHashKey_t:
    case DsUserIdIpv6SaHashKey_t:
    case DsUserIdIpv6DaHashKey_t:
    case DsUserIdMacHashKey_t:
    case DsUserIdMacPortHashKey_t:
    case DsUserIdPortHashKey_t:
    case DsUserIdSclFlowL2HashKey_t:
    case DsUserIdSclFlowL2UDFHashKey_t:
    case DsUserIdSclFlowL3UDFHashKey_t:
    case DsUserIdSvlanCosPortHashKey_t:
    case DsUserIdSvlanHashKey_t:
    case DsUserIdSvlanMacSaHashKey_t:
    case DsUserIdSvlanPortHashKey_t:
    case DsUserIdNshHashKey_t:
    case DsUserId0VlanPortDscpHashKey_t:
    case DsUserIdTunnelCapwapRmacHashKey_t:
    case DsUserIdTunnelCapwapRmacRidHashKey_t:
    case DsUserIdTunnelIpv4CapwapHashKey_t:
    case DsUserIdTunnelIpv4DaHashKey_t:
    case DsUserIdTunnelIpv4GreKeyHashKey_t:
    case DsUserIdTunnelIpv4HashKey_t:
    case DsUserIdTunnelIpv4McNvgreMode0HashKey_t:
    case DsUserIdTunnelIpv4McVxlanMode0HashKey_t:
    case DsUserIdTunnelIpv4NvgreMode1HashKey_t:
    case DsUserIdTunnelIpv4RpfHashKey_t:
    case DsUserIdTunnelIpv4UcNvgreMode0HashKey_t:
    case DsUserIdTunnelIpv4UcNvgreMode1HashKey_t:
    case DsUserIdTunnelIpv4UcVxlanMode0HashKey_t:
    case DsUserIdTunnelIpv4UcVxlanMode1HashKey_t:
    case DsUserIdTunnelIpv4UdpHashKey_t:
    case DsUserIdTunnelIpv4VxlanMode1HashKey_t:
    case DsUserIdTunnelIpv6DaHashKey_t:
    case DsUserIdTunnelIpv6GreKeyHashKey_t:
    case DsUserIdTunnelIpv6HashKey_t:
    case DsUserIdTunnelIpv6UdpHashKey_t:
    case DsUserIdTunnelIpv6CapwapHashKey_t:
    case DsUserIdTunnelIpv6McNvgreMode0HashKey_t:
    case DsUserIdTunnelIpv6McNvgreMode1HashKey_t:
    case DsUserIdTunnelIpv6McVxlanMode0HashKey_t:
    case DsUserIdTunnelIpv6McVxlanMode1HashKey_t:
    case DsUserIdTunnelIpv6UcNvgreMode0HashKey_t:
    case DsUserIdTunnelIpv6UcNvgreMode1HashKey_t:
    case DsUserIdTunnelIpv6UcVxlanMode0HashKey_t:
    case DsUserIdTunnelIpv6UcVxlanMode1HashKey_t:
    case DsUserIdTunnelMplsHashKey_t:
    case DsUserIdTunnelPbbHashKey_t:
    case DsUserIdTunnelTrillMcAdjHashKey_t:
    case DsUserIdTunnelTrillMcDecapHashKey_t:
    case DsUserIdTunnelTrillMcRpfHashKey_t:
    case DsUserIdTunnelTrillUcDecapHashKey_t:
    case DsUserIdTunnelTrillUcRpfHashKey_t:
    case DsUserId0TunnelIpv4CloudSecHashKey_t:
    case DsUserId0TunnelIpv6CloudSecHashKey_t:
        /**< [TM] */
    case DsUserId1CapwapMacDaForwardHashKey_t:
    case DsUserId1CapwapStaStatusHashKey_t:
    case DsUserId1CapwapStaStatusMcHashKey_t:
    case DsUserId1CapwapVlanForwardHashKey_t:
    case DsUserId1CvlanCosPortHashKey_t:
    case DsUserId1CvlanPortHashKey_t:
    case DsUserId1DoubleVlanPortHashKey_t:
    case DsUserId1EcidNameSpaceHashKey_t:
    case DsUserId1IngEcidNameSpaceHashKey_t:
    case DsUserId1Ipv4PortHashKey_t:
    case DsUserId1Ipv4SaHashKey_t:
    case DsUserId1Ipv4DaHashKey_t:
    case DsUserId1Ipv6PortHashKey_t:
    case DsUserId1Ipv6SaHashKey_t:
    case DsUserId1Ipv6DaHashKey_t:
    case DsUserId1MacHashKey_t:
    case DsUserId1MacPortHashKey_t:
    case DsUserId1PortHashKey_t:
    case DsUserId1SclFlowL2HashKey_t:
    case DsUserId1SclFlowL2UDFHashKey_t:
    case DsUserId1SclFlowL3UDFHashKey_t:
    case DsUserId1SvlanCosPortHashKey_t:
    case DsUserId1SvlanHashKey_t:
    case DsUserId1SvlanMacSaHashKey_t:
    case DsUserId1SvlanPortHashKey_t:
    case DsUserId1NshHashKey_t:
    case DsUserId1VlanPortDscpHashKey_t:
    case DsUserId1TunnelCapwapRmacHashKey_t:
    case DsUserId1TunnelCapwapRmacRidHashKey_t:
    case DsUserId1TunnelIpv4CapwapHashKey_t:
    case DsUserId1TunnelIpv4DaHashKey_t:
    case DsUserId1TunnelIpv4GreKeyHashKey_t:
    case DsUserId1TunnelIpv4HashKey_t:
    case DsUserId1TunnelIpv4McNvgreMode0HashKey_t:
    case DsUserId1TunnelIpv4McVxlanMode0HashKey_t:
    case DsUserId1TunnelIpv4NvgreMode1HashKey_t:
    case DsUserId1TunnelIpv4RpfHashKey_t:
    case DsUserId1TunnelIpv4UcNvgreMode0HashKey_t:
    case DsUserId1TunnelIpv4UcNvgreMode1HashKey_t:
    case DsUserId1TunnelIpv4UcVxlanMode0HashKey_t:
    case DsUserId1TunnelIpv4UcVxlanMode1HashKey_t:
    case DsUserId1TunnelIpv4UdpHashKey_t:
    case DsUserId1TunnelIpv4VxlanMode1HashKey_t:
    case DsUserId1TunnelIpv6DaHashKey_t:
    case DsUserId1TunnelIpv6GreKeyHashKey_t:
    case DsUserId1TunnelIpv6HashKey_t:
    case DsUserId1TunnelIpv6UdpHashKey_t:
    case DsUserId1TunnelIpv6CapwapHashKey_t:
    case DsUserId1TunnelIpv6McNvgreMode0HashKey_t:
    case DsUserId1TunnelIpv6McNvgreMode1HashKey_t:
    case DsUserId1TunnelIpv6McVxlanMode0HashKey_t:
    case DsUserId1TunnelIpv6McVxlanMode1HashKey_t:
    case DsUserId1TunnelIpv6UcNvgreMode0HashKey_t:
    case DsUserId1TunnelIpv6UcNvgreMode1HashKey_t:
    case DsUserId1TunnelIpv6UcVxlanMode0HashKey_t:
    case DsUserId1TunnelIpv6UcVxlanMode1HashKey_t:
    case DsUserId1TunnelTrillMcAdjHashKey_t:
    case DsUserId1TunnelTrillMcDecapHashKey_t:
    case DsUserId1TunnelTrillMcRpfHashKey_t:
    case DsUserId1TunnelTrillUcDecapHashKey_t:
    case DsUserId1TunnelTrillUcRpfHashKey_t:
    case DsUserId1TunnelIpv4CloudSecHashKey_t:
    case DsUserId1TunnelIpv6CloudSecHashKey_t:
    case DsUserId1XKeySingleHashKey_t:/*xkey*/
    case DsUserId1XKeyDoubleHashKey_t:/*xkey*/
    case DsUserId1XKeyQuadHashKey_t:/*xkey*/
    case DsUserId0XKeySingleHashKey_t:/*xkey*/
    case DsUserId0XKeyDoubleHashKey_t:/*xkey*/
    case DsUserId0XKeyQuadHashKey_t :/*xkey*/  
        *p_module = DRV_ACC_HASH_MODULE_USERID;
        break;

    case DsIpfixL2HashKey_t:
    case DsIpfixL2L3HashKey_t:
    case DsIpfixL3Ipv4HashKey_t:
    case DsIpfixL3Ipv4ShortHashKey_t:
    case DsIpfixL3Ipv4ShortHashKey0_t:
    case DsIpfixL3Ipv4ShortHashKey1_t:
    case DsIpfixL3Ipv6HashKey_t:
    case DsIpfixL3Ipv6ShortHashKey_t:
    case DsIpfixL3Ipv6ShortHashKey0_t:
    case DsIpfixL3Ipv6ShortHashKey1_t:
    case DsIpfixL3MplsHashKey_t:
    case DsIpfixUdfHashKey_t:
    case DsIpfixUdfShortHashKey_t:
    case DsIpfixUdfHashKey0_t:
    case DsIpfixUdfShortHashKey0_t:
    case DsIpfixUdfHashKey1_t:
    case DsIpfixUdfShortHashKey1_t:
    case DsIpfixSessionRecord_t:
    case DsIpfixSessionRecordMem0_t:
    case DsIpfixSessionRecordMem1_t:
    case DsIpfixL2HashKey0_t:
    case DsIpfixL2L3HashKey0_t:
    case DsIpfixL3Ipv4HashKey0_t:
    case DsIpfixL3Ipv6HashKey0_t:
    case DsIpfixL3MplsHashKey0_t:
    case DsIpfixSessionRecord0_t:
    case DsIpfixL2HashKey1_t:
    case DsIpfixL2L3HashKey1_t:
    case DsIpfixL3Ipv4HashKey1_t:
    case DsIpfixL3Ipv6HashKey1_t:
    case DsIpfixL3MplsHashKey1_t:
    case DsIpfixSessionRecord1_t:
    case DsIpfixSessionFullRecord0_t:
    case DsIpfixSessionFullRecord1_t:
    case DsIpfixSessionHalfRecord0_t:
    case DsIpfixSessionHalfRecord1_t:
        *p_module = DRV_ACC_HASH_MODULE_IPFIX;
        break;

    case DsMacLimitCount_t:
    case DsMacSecurity_t:
        *p_module = DRV_ACC_HASH_MODULE_MAC_LIMIT;
        break;

    case DsCategoryIdPairHashLeftKey_t:
    case DsCategoryIdPairHashRightKey_t:
        *p_module = DRV_ACC_HASH_MODULE_CID;
        break;

    case DsAging_t:
    case DsAgingStatusFib_t:
    case DsAgingStatusTcam_t:
        *p_module = DRV_ACC_HASH_MODULE_AGING;
        break;

    case DsMplsLabelHashKey_t:
        *p_module = DRV_ACC_HASH_MODULE_MPLS_HASH;
        break;
    case DsGemPortHashKey_t:
        *p_module = DRV_ACC_HASH_MODULE_GEMPORT_HASH;
        break;
    case DsQueueMapHashKey_t:
        *p_module = DRV_ACC_HASH_MODULE_QUEUE_MAP_HASH;
        break;
    case DsXSecRxL2MacsecHashKey_t:
    case DsXSecTxL3L4V4HashKey_t:
    case DsXSecRxL3L4V4HashKey_t:
    case DsXSecRxL3L4V6HashKey_t:
    case DsXSecTxL3L4V6HashKey_t:
    case DsXSecRxL2BasicHashKey_t:
    case DsXSecTxL2BasicHashKey_t:
    case DsXSecRxSpiHashKey_t:
    case DsXSecTxSpiHashKey_t:
        *p_module =   DRV_ACC_HASH_MODULE_DOT1AE;
        break;

    case DsXLookup0HashKey_t:
    case DsXLookup0MutationHashKey_t:
    case DsXLookup1HashKey_t:
        *p_module = DRV_ACC_HASH_MODULE_X_FLOW;
        break;

    default:
        return DRV_E_INVAILD_TYPE;
    }

    return DRV_E_NONE;
}

#define __ACC_FDB__

uint32
_drv_usw_hash_calculate_index(key_lookup_info_t * key_info, key_lookup_result_t * key_result)
{
    uint32 seed = 0xffffffff;
    uint8 * data = key_info->key_data;
    uint32 data_length = key_info->crc_bits;
    uint32 poly = 0 ;
    uint32 poly_len = 0;
    uint32 bucket_index = 0;
    if (0 == key_info->type)/*HASH_CRC*/
    {
        poly = key_info->polynomial;
        poly_len = key_info->poly_len;
        bucket_index = drv_hash_crc(seed,data,data_length,poly,poly_len);
    }
    else
    {
        bucket_index = drv_hash_xor16((uint16*) data, data_length);
    }

    key_result->bucket_index = bucket_index;
    return DRV_E_NONE;
}

#ifdef DUET2
STATIC int32
_drv_usw_host0_calc_fdb_index(uint8 lchip, drv_acc_in_t* in, drv_acc_out_t* out)
{
#define HASH_LEVEL_NUM 6

    drv_acc_in_t  host0_in;
    drv_acc_out_t host0_out;
    key_lookup_info_t key_info;
    uint8 level = 0;
    uint8 index = 0;
    int32 ret = 0;
    uint32 bucket_num = 4;/*only for fib_host0*/
    key_lookup_result_t  key_result;
    uint32 rslt_index = 0;
    FibHost0HashLookupCtl_m hash_lookup_ctl;
    uint8 key[MAX_ENTRY_BYTE] = {0};
    uint8 poly_type[HASH_LEVEL_NUM] = {0};
    uint8 level_en[HASH_LEVEL_NUM] = {0};
    uint32 index_base[HASH_LEVEL_NUM] = {0};
    uint32 key_index = 0;
    uint32 hw_hashtype = 0;
    uint32 crc[][3]= { /*refer to fib_host0_crc*/
         {0, 0x00000005, 11},/*HASH_CRC*/
         {0, 0x00000017, 11},/*HASH_CRC*/
         {0, 0x0000002b, 11},/*HASH_CRC*/
         {0, 0x00000053, 12},/*HASH_CRC*/
         {0, 0x00000099, 12},/*HASH_CRC*/
         {0, 0x00000107, 12},/*HASH_CRC*/
         {0, 0x0000001b, 13},/*HASH_CRC*/
         {0, 0x00000027, 13},/*HASH_CRC*/
         {0, 0x000000c3, 13},/*HASH_CRC*/
         {1, 16        , 0}, /*HASH_XOR*/
      };

    if (in->tbl_id != DsFibHost0MacHashKey_t)
    {
        return DRV_E_INVALID_TBL;
    }

    sal_memset(&hash_lookup_ctl, 0, sizeof(FibHost0HashLookupCtl_m));
    sal_memset(&key_info, 0, sizeof(key_lookup_info_t));
    sal_memset(&key_result, 0, sizeof(key_lookup_result_t));


    DRV_APP_REG_IOR(lchip,FibHost0HashLookupCtl_t,&hash_lookup_ctl,DRV_ACC_PP_EN);
    level_en[0] = GetFibHost0HashLookupCtl(V, fibHost0Level0HashEn_f, &hash_lookup_ctl);
    level_en[1] = GetFibHost0HashLookupCtl(V, fibHost0Level1HashEn_f, &hash_lookup_ctl);
    level_en[2] = GetFibHost0HashLookupCtl(V, fibHost0Level2HashEn_f, &hash_lookup_ctl);
    level_en[3] = GetFibHost0HashLookupCtl(V, fibHost0Level3HashEn_f, &hash_lookup_ctl);
    level_en[4] = GetFibHost0HashLookupCtl(V, fibHost0Level4HashEn_f, &hash_lookup_ctl);
    level_en[5] = GetFibHost0HashLookupCtl(V, fibHost0Level5HashEn_f, &hash_lookup_ctl);
    index_base[1] = GetFibHost0HashLookupCtl(V, fibHost0Level1IndexBase_f, &hash_lookup_ctl);
    index_base[2] = GetFibHost0HashLookupCtl(V, fibHost0Level2IndexBase_f, &hash_lookup_ctl);
    index_base[3] = GetFibHost0HashLookupCtl(V, fibHost0Level3IndexBase_f, &hash_lookup_ctl);
    index_base[4] = GetFibHost0HashLookupCtl(V, fibHost0Level4IndexBase_f, &hash_lookup_ctl);
    index_base[5] = GetFibHost0HashLookupCtl(V, fibHost0Level5IndexBase_f, &hash_lookup_ctl);
    poly_type[0] = GetFibHost0HashLookupCtl(V, fibHost0Level0HashType_f, &hash_lookup_ctl);
    poly_type[1] = GetFibHost0HashLookupCtl(V, fibHost0Level1HashType_f, &hash_lookup_ctl);
    poly_type[2] = GetFibHost0HashLookupCtl(V, fibHost0Level2HashType_f, &hash_lookup_ctl);
    poly_type[3] = GetFibHost0HashLookupCtl(V, fibHost0Level3HashType_f, &hash_lookup_ctl);
    poly_type[4] = GetFibHost0HashLookupCtl(V, fibHost0Level4HashType_f, &hash_lookup_ctl);
    poly_type[5] = GetFibHost0HashLookupCtl(V, fibHost0Level5HashType_f, &hash_lookup_ctl);

    key_info.key_data = key;
    sal_memcpy(key_info.key_data, (uint8*)in->data, sizeof(DsFibHost0MacHashKey_m));
    key_info.crc_bits = 170;/*always 170 for host0, refer to gg_hash_key_length*/
    key_info.key_bits = 85;

    host0_in.tbl_id    = DsFibHost0MacHashKey_t;
    host0_in.op_type = DRV_ACC_OP_BY_INDEX;
    host0_in.type = DRV_ACC_TYPE_LOOKUP;
    host0_in.module = DRV_ACC_HASH_MODULE_FDB;

    for (level = 0; level < HASH_LEVEL_NUM; level++)
    {
        if (level_en[level] == 0)
        {
            continue;
        }
        key_info.type       = crc[poly_type[level]][0];
        key_info.polynomial = crc[poly_type[level]][1];
        key_info.poly_len   = crc[poly_type[level]][2];
        _drv_usw_hash_calculate_index(&key_info, &key_result);
        rslt_index = index_base[level] + key_result.bucket_index * bucket_num + 32;
        for (index = 0; index < bucket_num; index++)
        {
            key_index = (rslt_index & 0xFFFFFFFC) | index;
             /*check if hashtype*/
            host0_in.index = key_index ;
            DRV_IF_ERROR_RETURN(drv_acc_api(lchip, &host0_in, &host0_out));
            hw_hashtype = GetDsFibHost0MacHashKey(V, hashType_f, &host0_out.data);
            if (hw_hashtype != 4)
            {
                continue;
            }
            out->data[out->query_cnt++] = key_index;
        }
    }

    return ret;
}
#endif

#ifdef TSINGMA
STATIC int32
_drv_usw_host0_calc_fdb_index_tsingma(uint8 lchip, drv_acc_in_t* in, drv_acc_out_t* out)
{
#undef HASH_LEVEL_NUM
#define HASH_LEVEL_NUM 10

    key_lookup_info_t key_info;
    uint8 level = 0;
    uint8 index = 0;
    int32 ret = 0;
    uint32 cmd = 0;
    uint32 bucket_num = 4;/*only for fib_host0*/
    key_lookup_result_t  key_result;
    uint32 rslt_index = 0;
    FibHost0HashLookupCtl_m hash_lookup_ctl;
    FibHost0ExternalHashLookupCtl_m extern_hash_ctl;
    uint8 key[MAX_ENTRY_BYTE] = {0};
    uint8 poly_type[HASH_LEVEL_NUM] = {0};
    uint8 level_en[HASH_LEVEL_NUM] = {0};
    uint32 index_base[HASH_LEVEL_NUM] = {0};
    uint32 key_index = 0;
    uint32 field_val = 0;
    uint8 couple_en = 0;
    uint32 crc[][3]= { /*refer to fib_host0_crc*/
         {0, 0x0000001b, 10},
         {0, 0x00000017, 11},
         {0, 0x0000002b, 11},
         {0, 0x00000053, 12},
         {0, 0x00000099, 12},
         {0, 0x00000107, 12},
         {0, 0x0000001b, 13},
         {0, 0x00000027, 13},
         {0, 0x00000053, 13},
         {0, 0x000000c3, 13},
         {0, 0x0000005f, 14},
         {0, 0x0000007b, 14},
         {0, 0x000000af, 14},
         {0, 0x000000bb, 14},
         {1, 16        , 0},
      };

    DRV_APP_REG_IOR(lchip,FibHost0HashLookupCtl_t,&hash_lookup_ctl,DRV_ACC_PP_EN);
    if(ret != 0) return ret;

    level_en[0] = GetFibHost0HashLookupCtl(V, fibHost0Level0HashEn_f, &hash_lookup_ctl) &&
                  GetFibHost0HashLookupCtl(V, fibHost0Level0MacKeyEn_f, &hash_lookup_ctl);

    level_en[1] = GetFibHost0HashLookupCtl(V, fibHost0Level1HashEn_f, &hash_lookup_ctl) &&
                  GetFibHost0HashLookupCtl(V, fibHost0Level1MacKeyEn_f, &hash_lookup_ctl);

    level_en[2] = GetFibHost0HashLookupCtl(V, fibHost0Level2HashEn_f, &hash_lookup_ctl) &&
                  GetFibHost0HashLookupCtl(V, fibHost0Level2MacKeyEn_f, &hash_lookup_ctl);

    level_en[3] = GetFibHost0HashLookupCtl(V, fibHost0Level3HashEn_f, &hash_lookup_ctl) &&
                  GetFibHost0HashLookupCtl(V, fibHost0Level3MacKeyEn_f, &hash_lookup_ctl);

    level_en[4] = GetFibHost0HashLookupCtl(V, fibHost0Level4HashEn_f, &hash_lookup_ctl) &&
                  GetFibHost0HashLookupCtl(V, fibHost0Level4MacKeyEn_f, &hash_lookup_ctl);

    level_en[5] = GetFibHost0HashLookupCtl(V, fibHost0Level5HashEn_f, &hash_lookup_ctl) &&
                  GetFibHost0HashLookupCtl(V, fibHost0Level5MacKeyEn_f, &hash_lookup_ctl);

    index_base[1] = GetFibHost0HashLookupCtl(V, fibHost0Level1IndexBase_f, &hash_lookup_ctl);
    index_base[2] = GetFibHost0HashLookupCtl(V, fibHost0Level2IndexBase_f, &hash_lookup_ctl);
    index_base[3] = GetFibHost0HashLookupCtl(V, fibHost0Level3IndexBase_f, &hash_lookup_ctl);
    index_base[4] = GetFibHost0HashLookupCtl(V, fibHost0Level4IndexBase_f, &hash_lookup_ctl);
    index_base[5] = GetFibHost0HashLookupCtl(V, fibHost0Level5IndexBase_f, &hash_lookup_ctl);
    poly_type[0] = GetFibHost0HashLookupCtl(V, fibHost0Level0HashType_f, &hash_lookup_ctl);
    poly_type[1] = GetFibHost0HashLookupCtl(V, fibHost0Level1HashType_f, &hash_lookup_ctl);
    poly_type[2] = GetFibHost0HashLookupCtl(V, fibHost0Level2HashType_f, &hash_lookup_ctl);
    poly_type[3] = GetFibHost0HashLookupCtl(V, fibHost0Level3HashType_f, &hash_lookup_ctl);
    poly_type[4] = GetFibHost0HashLookupCtl(V, fibHost0Level4HashType_f, &hash_lookup_ctl);
    poly_type[5] = GetFibHost0HashLookupCtl(V, fibHost0Level5HashType_f, &hash_lookup_ctl);


    cmd = DRV_IOR(FibEngineLookupCtl_t, FibEngineLookupCtl_externalLookupEn_f);
    DRV_IF_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0,  cmd, &field_val));
    level_en[6] = field_val;
    level_en[7] = field_val;
    level_en[8] = field_val;
    level_en[9] = field_val;



    DRV_APP_REG_IOR(lchip,FibHost0ExternalHashLookupCtl_t,&extern_hash_ctl,DRV_ACC_PP_EN);
    if(ret != 0) return ret;

    couple_en = GetFibHost0ExternalHashLookupCtl(V, externalMemoryCouple_f, &extern_hash_ctl);
    index_base[6] = GetFibHost0ExternalHashLookupCtl(V, externalKeyIndexBase_f, &extern_hash_ctl) - 32;
    index_base[7] =  index_base[6] + ((couple_en?2:1) <<15) ;
    index_base[8] =  index_base[7] + ((couple_en?2:1) <<15) ;
    index_base[9] =  index_base[8] + ((couple_en?2:1) <<15) ;

    poly_type[6] = GetFibHost0ExternalHashLookupCtl(V, externalLevel0HashType_f, &extern_hash_ctl);
    poly_type[7] = GetFibHost0ExternalHashLookupCtl(V, externalLevel1HashType_f, &extern_hash_ctl);
    poly_type[8] = GetFibHost0ExternalHashLookupCtl(V, externalLevel2HashType_f, &extern_hash_ctl);
    poly_type[9] = GetFibHost0ExternalHashLookupCtl(V, externalLevel3HashType_f, &extern_hash_ctl);

    key_info.key_data = key;
    sal_memcpy(key_info.key_data, (uint8*)in->data, sizeof(DsFibHost0MacHashKey_m));
    key_info.crc_bits = 170;/*always 170 for host0, refer to gg_hash_key_length*/
    key_info.key_bits = 85;

    for (level = 0; level < HASH_LEVEL_NUM; level++)
    {
        if (level_en[level] == 0 || (in->level == level))
        {
            continue;
        }
        key_info.type       = crc[poly_type[level]][0];
        key_info.polynomial = crc[poly_type[level]][1];
        key_info.poly_len   = crc[poly_type[level]][2];
        _drv_usw_hash_calculate_index(&key_info, &key_result);
        rslt_index = index_base[level] + key_result.bucket_index * bucket_num + 32;
        for (index = 0; index < bucket_num; index++)
        {
            key_index = (rslt_index & 0xFFFFFFFC) | index;
            out->data[out->query_cnt] = key_index;
            out->out_level[out->query_cnt++] = level;
        }
    }

    return ret;
}
#endif

#if defined(TSINGMA_MX) || defined(TSINGMA_GX)
extern int32 drv_tmm_app_api_init(uint8 lchip);
STATIC int32
_drv_usw_host0_calc_fdb_index_tsingma_mx(uint8 lchip, drv_acc_in_t* in, drv_acc_out_t* out)
{
#undef HASH_LEVEL_NUM
#define HASH_LEVEL_NUM 7

    key_lookup_info_t key_info;
    uint8 level = 0;
    uint8 index = 0;
    int32 ret = 0;
    uint32 bucket_num = 4;/*only for fib_host0*/
    key_lookup_result_t  key_result;
    uint32 rslt_index = 0;
    FibHost0HashLookupCtl_m hash_lookup_ctl;
    uint8 key[MAX_ENTRY_BYTE] = {0};
    uint8 poly_type[HASH_LEVEL_NUM] = {0};
    uint8 level_en[HASH_LEVEL_NUM] = {0};
    uint32 index_base[HASH_LEVEL_NUM] = {0};
    uint32 key_index = 0;

    uint32 crc[][3]= { //CRC
         {0, 0x00000053, 12},
         {0, 0x00000099, 12},
         {0, 0x00000053, 13},
         {0, 0x000000c3, 13},
         {0, 0x0000007b, 14},
         {0, 0x000000af, 14},
         {0, 0x000000bb, 14},
         {0, 0x0000005f, 14},
         {0, 0x000000cf, 14},
         {0, 0x00000003, 15},
         {0, 0x00000011, 15},
         {0, 0x00000081, 15},
         {0, 0x0000002d, 15},
         {0, 0x00000035, 15},
         {0, 0x0000002b, 11},
         {0, 0x00000017, 11},
         {0, 0x00000069, 12},
         {0, 0x000000d1, 12},
      };

    DRV_APP_REG_IOR(lchip,FibHost0HashLookupCtl_t,&hash_lookup_ctl,DRV_ACC_PP_EN);
    if(ret != 0) return ret;

    level_en[0] = GetFibHost0HashLookupCtl(V, fibHost0L2Level0HashEn_f, &hash_lookup_ctl);
    level_en[1] = GetFibHost0HashLookupCtl(V, fibHost0L2Level1HashEn_f, &hash_lookup_ctl);
    level_en[2] = GetFibHost0HashLookupCtl(V, fibHost0L2Level2HashEn_f, &hash_lookup_ctl);
    level_en[3] = GetFibHost0HashLookupCtl(V, fibHost0L2Level3HashEn_f, &hash_lookup_ctl);
    level_en[4] = GetFibHost0HashLookupCtl(V, fibHost0L2Level4HashEn_f, &hash_lookup_ctl);
    level_en[5] = GetFibHost0HashLookupCtl(V, fibHost0L2Level5HashEn_f, &hash_lookup_ctl);
    level_en[6] = GetFibHost0HashLookupCtl(V, fibHost0L2Level6HashEn_f, &hash_lookup_ctl);

    index_base[0] = 0;
    index_base[1] = GetFibHost0HashLookupCtl(V, fibHost0L2Level1IndexBase_f, &hash_lookup_ctl);
    index_base[2] = GetFibHost0HashLookupCtl(V, fibHost0L2Level2IndexBase_f, &hash_lookup_ctl);
    index_base[3] = GetFibHost0HashLookupCtl(V, fibHost0L2Level3IndexBase_f, &hash_lookup_ctl);
    index_base[4] = GetFibHost0HashLookupCtl(V, fibHost0L2Level4IndexBase_f, &hash_lookup_ctl);
    index_base[5] = GetFibHost0HashLookupCtl(V, fibHost0L2Level5IndexBase_f, &hash_lookup_ctl);
    index_base[6] = GetFibHost0HashLookupCtl(V, fibHost0L2Level6IndexBase_f, &hash_lookup_ctl);

    poly_type[0] = GetFibHost0HashLookupCtl(V, fibHost0L2Level0HashType_f, &hash_lookup_ctl);
    poly_type[1] = GetFibHost0HashLookupCtl(V, fibHost0L2Level1HashType_f, &hash_lookup_ctl);
    poly_type[2] = GetFibHost0HashLookupCtl(V, fibHost0L2Level2HashType_f, &hash_lookup_ctl);
    poly_type[3] = GetFibHost0HashLookupCtl(V, fibHost0L2Level3HashType_f, &hash_lookup_ctl);
    poly_type[4] = GetFibHost0HashLookupCtl(V, fibHost0L2Level4HashType_f, &hash_lookup_ctl);
    poly_type[5] = GetFibHost0HashLookupCtl(V, fibHost0L2Level5HashType_f, &hash_lookup_ctl);
    poly_type[6] = GetFibHost0HashLookupCtl(V, fibHost0L2Level6HashType_f, &hash_lookup_ctl);


    key_info.key_data = key;
    sal_memcpy(key_info.key_data, (uint8*)in->data, sizeof(DsFibHost0MacHashKey_m));
    key_info.crc_bits = 174;
    key_info.key_bits = 87;

    for (level = 0; level < HASH_LEVEL_NUM; level++)
    {
        if (level_en[level] == 0 || (in->level == level))
        {
            continue;
        }
        key_info.type       = crc[poly_type[level]][0];
        key_info.polynomial = crc[poly_type[level]][1];
        key_info.poly_len   = crc[poly_type[level]][2];
        _drv_usw_hash_calculate_index(&key_info, &key_result);
        rslt_index = index_base[level] + key_result.bucket_index * bucket_num + 32;
        for (index = 0; index < bucket_num; index++)
        {
            key_index = (rslt_index & 0xFFFFFFFC) | index;
            out->data[out->query_cnt] = key_index;
            out->out_level[out->query_cnt++] = level;
        }
    }

    return DRV_E_NONE;
}
#endif

#ifdef ARCTIC
extern int32 drv_at_app_api_init(uint8 lchip);
STATIC int32
_drv_usw_host0_calc_fdb_index_arctic(uint8 lchip, drv_acc_in_t* in, drv_acc_out_t* out)
{
#undef HASH_LEVEL_NUM
#define HASH_LEVEL_NUM 6

    key_lookup_info_t key_info;
    uint8 level = 0;
    uint8 index = 0;
    int32 ret = 0;
    uint32 bucket_num = 4;/*only for fib_host0*/
    key_lookup_result_t  key_result;
    uint32 rslt_index = 0;
    FibHost0HashLookupCtl_m hash_lookup_ctl;
    uint8 key[MAX_ENTRY_BYTE] = {0};
    uint8 poly_type[HASH_LEVEL_NUM] = {0};
    uint8 level_en[HASH_LEVEL_NUM] = {0};
    uint32 index_base[HASH_LEVEL_NUM] = {0};
    uint32 key_index = 0;

    uint32 crc[][3]= { //CRC
         {0, 0x00000053, 12},
         {0, 0x00000099, 12},
         {0, 0x00000053, 13},
         {0, 0x000000c3, 13},
         {0, 0x000000c9, 13},
         {0, 0x000000e1, 13},
         {0, 0x0000007b, 14},
         {0, 0x000000af, 14},
         {0, 0x000000bb, 14},
         {0, 0x0000005f, 14},
         {0, 0x00000081, 15},
         {0, 0x0000002d, 15},
         {0, 0x00000069, 12},
         {0, 0x000000d1, 12},
         {0, 0x000000f3, 13},
         {0, 0x0000010d, 13}
      };

    DRV_APP_REG_IOR(lchip,FibHost0HashLookupCtl_t,&hash_lookup_ctl,DRV_ACC_PP_EN);
    if(ret != 0) return ret;

    level_en[0] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_0_hashEn_f, &hash_lookup_ctl);
    level_en[1] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_1_hashEn_f, &hash_lookup_ctl);
    level_en[2] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_2_hashEn_f, &hash_lookup_ctl);
    level_en[3] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_3_hashEn_f, &hash_lookup_ctl);
    level_en[4] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_4_hashEn_f, &hash_lookup_ctl);
    level_en[5] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_5_hashEn_f, &hash_lookup_ctl);
    

    index_base[0] = 0;
    index_base[1] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_1_indexBase_f, &hash_lookup_ctl);
    index_base[2] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_2_indexBase_f, &hash_lookup_ctl);
    index_base[3] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_3_indexBase_f, &hash_lookup_ctl);
    index_base[4] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_4_indexBase_f, &hash_lookup_ctl);
    index_base[5] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_5_indexBase_f, &hash_lookup_ctl);
    

    poly_type[0] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_0_hashType_f, &hash_lookup_ctl);
    poly_type[1] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_1_hashType_f, &hash_lookup_ctl);
    poly_type[2] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_2_hashType_f, &hash_lookup_ctl);
    poly_type[3] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_3_hashType_f, &hash_lookup_ctl);
    poly_type[4] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_4_hashType_f, &hash_lookup_ctl);
    poly_type[5] = GetFibHost0HashLookupCtl(V, fibHost0L2Level_5_hashType_f, &hash_lookup_ctl);
    

    key_info.key_data = key;
    sal_memcpy(key_info.key_data, (uint8*)in->data, sizeof(DsFibHost0MacHashKey_m));
    key_info.crc_bits = 176;
    key_info.key_bits = 88;

    for (level = 0; level < HASH_LEVEL_NUM; level++)
    {
        if (level_en[level] == 0 || (in->level == level))
        {
            continue;
        }
        key_info.type       = crc[poly_type[level]][0];
        key_info.polynomial = crc[poly_type[level]][1];
        key_info.poly_len   = crc[poly_type[level]][2];
        #if (SDK_WORK_PLATFORM == 1)
        if (g_mem_fib_hashkey_cutdown > 1)
        {
            uint8 ii = 0;
            while ((g_mem_fib_hashkey_cutdown >> (++ii)) != 1);
            if (ii <= 12)
            {
                key_info.poly_len -= ii;
            }
        }
        #endif
        _drv_usw_hash_calculate_index(&key_info, &key_result);
        rslt_index = index_base[level] + key_result.bucket_index * bucket_num + 32;
        for (index = 0; index < bucket_num; index++)
        {
            key_index = (rslt_index & 0xFFFFFFFC) | index;
            out->data[out->query_cnt] = key_index;
            out->out_level[out->query_cnt++] = level;
        }
    }

    return DRV_E_NONE;
}
#endif


STATIC int32
_drv_usw_acc_prepare_null(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
   return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_write_mac_by_idx(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    hw_mac_addr_t   mac = {0};
    uint16 fid = 0;
    uint32 ad_idx = 0;
    DsFibHost0MacHashKey_m* p_mac_key = NULL;
    uint32 req_type = DRV_ACC_CHIP_MAC_WRITE_BY_INDEX;

    p_mac_key = (DsFibHost0MacHashKey_m*)in->data;

    GetDsFibHost0MacHashKey(A, mappedMac_f, p_mac_key, mac);
    fid = GetDsFibHost0MacHashKey(V, vsiId_f, p_mac_key);
    ad_idx = GetDsFibHost0MacHashKey(V, dsAdIndex_f, p_mac_key);

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, req_type);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, mac);
    SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, cpu_req, fid);
    SetFibHashKeyCpuReq(V, cpuKeyDsAdIndex_f, cpu_req, ad_idx);
    SetFibHashKeyCpuReq(V, cpuKeyIndex_f, cpu_req, in->index);
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_write_mac_by_key(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    uint32 key_index       = 0;
    uint32 static_count_en = 0;
    uint32 hw_aging_en = 0;
    hw_mac_addr_t   mac = {0};
    uint16 fid = 0;
    uint32 ad_idx = 0;
    DsFibHost0MacHashKey_m* p_mac_key = NULL;
    uint32 req_type = DRV_ACC_CHIP_MAC_WRITE_BY_KEY;
    DRV_PTR_VALID_CHECK(in->data);

    p_mac_key = (DsFibHost0MacHashKey_m*)in->data;

    GetDsFibHost0MacHashKey(A, mappedMac_f, p_mac_key, mac);
    fid = GetDsFibHost0MacHashKey(V, vsiId_f, p_mac_key);
    ad_idx = GetDsFibHost0MacHashKey(V, dsAdIndex_f, p_mac_key);

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_UPDATE_MAC_LIMIT_CNT))
    {
        key_index |= 1 << 14;    /* port mac limit */
        key_index |= 1 << 15;    /* vlan mac limit */

        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC))
        {
            key_index |= 1 << 16;    /* dynamic mac limit */
        }
    }

    if (DRV_IS_BIT_SET(in->flag, DRC_ACC_PROFILE_MAC_LIMIT_EN))
    {
        key_index |= 1 << 17;    /* profile mac limit */
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
    {
        /*logic port do not update port mac limit*/
        key_index &= ~(1<<14);
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_STATIC_MAC_LIMIT_CNT))
    {
        static_count_en = 1;
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_AGING_EN))
    {
        hw_aging_en = 1;
    }

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, req_type);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, mac);
    SetFibHashKeyCpuReq(V, staticCountEn_f, cpu_req, static_count_en);
    SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, cpu_req, fid);
    SetFibHashKeyCpuReq(V, cpuKeyDsAdIndex_f, cpu_req, ad_idx);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqPort_f, cpu_req, in->gport);
    SetFibHashKeyCpuReq(V, cpuKeyIndex_f, cpu_req, key_index);
    SetFibHashKeyCpuReq(V, cpuKeyDelType_f, cpu_req, in->timer_index);
    SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, cpu_req, hw_aging_en);

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_del_mac_by_idx(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_MAC_DEL_BY_INDEX);
    SetFibHashKeyCpuReq(V, cpuKeyIndex_f, cpu_req, in->index);
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_del_mac_by_key(uint8 lchip, drv_acc_in_t* in, uint32* cpu_req)
{
    uint32 key_index = 0;
    hw_mac_addr_t   mac = {0};
    uint16 fid = 0;
    DsFibHost0MacHashKey_m* p_mac_key = NULL;
    p_mac_key = (DsFibHost0MacHashKey_m*)in->data;

    GetDsFibHost0MacHashKey(A, mappedMac_f, p_mac_key, mac);
    fid = GetDsFibHost0MacHashKey(V, vsiId_f, p_mac_key);

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_UPDATE_MAC_LIMIT_CNT))
    {
        key_index |= 1 << 14;    /* port mac limit */
        key_index |= 1 << 15;    /* vlan mac limit */
        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC))
        {
            key_index |= 1 << 16;    /* dynamic mac limit */
        }
    }

    if (DRV_IS_BIT_SET(in->flag, DRC_ACC_PROFILE_MAC_LIMIT_EN))
    {
        key_index |= 1 << 17;    /* profile mac limit */
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
    {
        /*logic port do not update port mac limit*/
        key_index &= ~(1<<14);
    }

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_MAC_DEL_BY_KEY);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, mac);
    SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, cpu_req, fid);
    SetFibHashKeyCpuReq(V, cpuKeyIndex_f, cpu_req, key_index);

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_lkp_mac_by_key(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    uint16 fid = 0;
    DsFibHost0MacHashKey_m* p_mac_key = NULL;
    hw_mac_addr_t   mac = {0};

    p_mac_key = (DsFibHost0MacHashKey_m*)in->data;

    GetDsFibHost0MacHashKey(A, mappedMac_f, p_mac_key, mac);
    fid = GetDsFibHost0MacHashKey(V, vsiId_f, p_mac_key);

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_MAC_LOOKUP_BY_KEY);
    SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, cpu_req, fid);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, mac);

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_dump(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    uint32        del_type  = 0;
    uint32        del_mode  = 0;
    uint32        key_index = 0;
    hw_mac_addr_t hw_mac    = { 0 };
    uint16 fid = 0;
    DsFibHost0MacHashKey_m* p_mac_key = NULL;
    uint32 req_type = 0;

    if (DRV_IS_DUET2(lchip)
         || DRV_IS_TSINGMA(lchip))
     {
         hw_mac[0] = (in->index & 0x7FFFF) |
                     ((in->query_end_index & 0x1f) << 19) |
                     (((in->query_end_index >> 5) & 0xff) << 24);

         hw_mac[1] = (in->query_end_index >> 13) & 0x3F;
     }
     else
     {
         hw_mac[0] = (in->index & 0x1FFFFF) |
                     ((in->query_end_index & 0x7) << 21) |
                     (((in->query_end_index >> 3) & 0xff) << 24);

         hw_mac[1] = (in->query_end_index >> 11) & 0x3FF;
     }

     key_index |= 1<<4;   /*Dump no pending*/
      if(in->op_type == DRV_ACC_OP_BY_ALL)
      {
         req_type = DRV_ACC_CHIP_MAC_FLUSH_DUMP_BY_ALL;
         del_mode = 1;

          if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_UCAST))
          {
              key_index |= 1<<2;
          }
         if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_MCAST))
          {
              key_index |= 1 << 3;
          }
          if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_PENDING))
          {
              key_index &= ~(1 << 4); /*do not dump no-pending*/
              key_index |= 1 << 5;
          }
      }
      else
      {
          req_type = DRV_ACC_CHIP_MAC_DUMP_BY_PORT_VLAN;
          if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
          {
             del_mode = 1;
              key_index |= (1 << 3);
          }
          if (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_VLAN))
           {    /*dump by port+vsi*/
               del_type = 0;
           }
           else if (in->op_type == DRV_ACC_OP_BY_PORT)
           {    /*dump by port*/
               del_type = 1;
           }
           else if (in->op_type == DRV_ACC_OP_BY_VLAN)
           {    /*dump by vsi*/
               del_type = 2;
           }

     }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_STATIC))
    {
        key_index |= 1;
    }
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC))
    {
        key_index |= 1 << 1;
    }

    p_mac_key = (DsFibHost0MacHashKey_m*)in->data;
    fid = GetDsFibHost0MacHashKey(V, vsiId_f, p_mac_key);

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, req_type);
    SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, cpu_req, fid);
    SetFibHashKeyCpuReq(V, cpuKeyDelType_f, cpu_req, del_type);
    SetFibHashKeyCpuReq(V, cpuKeyIndex_f, cpu_req, key_index);
    SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, cpu_req, del_mode);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqPort_f, cpu_req, in->gport);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, hw_mac);
    SetFibHashKeyCpuReq(V, cpuKeyDsAdIndex_f, cpu_req, in->query_cnt);
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_flex(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    int32        ret   = 0;
    hw_mac_addr_t hw_mac    = { 0 };
    hw_mac_addr_t mac    = { 0 };
    hw_mac_addr_t hw_mac_mask    = { 0 };
    uint16 fid = 0;
    uint8 acc_type = 0;
    uint32 key_index = 0;
    DsFibHost0MacHashKey_m* p_mac_key = NULL;
    FibAccelerationData_m acc_data;

    sal_memset(&acc_data, 0, sizeof(FibAccelerationData_m));
    p_mac_key = (DsFibHost0MacHashKey_m*)in->data;
    GetDsFibHost0MacHashKey(A, mappedMac_f, p_mac_key, mac);
    fid = GetDsFibHost0MacHashKey(V, vsiId_f, p_mac_key);

    /*
        ONLY support flush/dump now, not support replace and count.
        FLEX TYPE: cpuKeyMac(43,42): 1=flash, 2=dump, 3=replace, 0=count
        START INDEX: cpuKeyMac(20,0)
        END INDEX: cpuKeyMac(41,21)
    */

    if (in->type == DRV_ACC_TYPE_DUMP_FLEX)
    {
        acc_type = 2;
    }
    else if (in->type == DRV_ACC_TYPE_FLUSH_FLEX)
    {
        acc_type = 1;
        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_UPDATE_MAC_LIMIT_CNT))
        {
            key_index |= 1 << 5;
            key_index |= 1 << 7;
            key_index |= 1 << 11;
        }
        /*profile*/
        key_index |= 1 << 9;
        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_STATIC_MAC_LIMIT_CNT))
        {
            key_index |= 1 << 4;
            key_index |= 1 << 6;
            key_index |= 1 << 8;
        }
        key_index |= 1 << 10;
        key_index |= 1 << 12;
    }
    else
    {
        return DRV_E_INVAILD_TYPE;  /* flex replace/count not support now */
    }

    hw_mac[0] = (in->index & 0x1FFFFF) |
                ((in->query_end_index & 0x7) << 21) |
                (((in->query_end_index >> 3) & 0xff) << 24);

    hw_mac[1] = ((in->query_end_index >> 11) & 0x3FF) |(acc_type << 10);

    if (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_VLAN))
    {
        SetFibAccelerationData(V, macKey_vsiId_f, &acc_data, fid);
        SetFibAccelerationData(V, macKeyMask_vsiId_f, &acc_data, 0x7FFF);
        SetFibAccelerationData(V, macAd_u2_g1_globalSrcPort_f, &acc_data, in->gport);
        SetFibAccelerationData(V, macAdMask_u2_g1_globalSrcPort_f, &acc_data, 0xFFFF);
        SetFibAccelerationData(V, macAd_learnSource_f, &acc_data, (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT)) ? 1 : 0);
        SetFibAccelerationData(V, macAdMask_learnSource_f, &acc_data, 1);
    }
    else if (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_MAC))
    {
        sal_memset(&hw_mac_mask, 0xFF, sizeof(hw_mac_addr_t));
        SetFibAccelerationData(V, macAd_u2_g1_globalSrcPort_f, &acc_data, in->gport);
        SetFibAccelerationData(V, macAdMask_u2_g1_globalSrcPort_f, &acc_data, 0xFFFF);
        SetFibAccelerationData(A, macKey_mappedMac_f, &acc_data, mac);
        SetFibAccelerationData(A, macKeyMask_mappedMac_f, &acc_data, hw_mac_mask);
        SetFibAccelerationData(V, macAd_learnSource_f, &acc_data, (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT)) ? 1 : 0);
        SetFibAccelerationData(V, macAdMask_learnSource_f, &acc_data, 1);
    }
    else if (in->op_type == DRV_ACC_OP_BY_MAC)
    {
        sal_memset(&hw_mac_mask, 0xFF, sizeof(hw_mac_addr_t));
        SetFibAccelerationData(A, macKey_mappedMac_f, &acc_data, mac);
        SetFibAccelerationData(A, macKeyMask_mappedMac_f, &acc_data, hw_mac_mask);
    }
    else if (in->op_type == DRV_ACC_OP_BY_PORT)
    {
        SetFibAccelerationData(V, macAd_u2_g1_globalSrcPort_f, &acc_data, in->gport);
        SetFibAccelerationData(V, macAdMask_u2_g1_globalSrcPort_f, &acc_data, 0xFFFF);
        SetFibAccelerationData(V, macAd_learnSource_f, &acc_data, (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT)) ? 1 : 0);
        SetFibAccelerationData(V, macAdMask_learnSource_f, &acc_data, 1);
    }
    else if (in->op_type == DRV_ACC_OP_BY_VLAN)
    {
        SetFibAccelerationData(V, macKey_vsiId_f, &acc_data, fid);
        SetFibAccelerationData(V, macKeyMask_vsiId_f, &acc_data, 0x7FFF);
    }
    else if (in->op_type == DRV_ACC_OP_BY_ALL)
    {
        /* KeyMask = 0, AdMask = 0 */
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_LOCAL_DYNAMIC)) 
    {
        DRV_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC);
        SetFibAccelerationData(V, macAd_userDefine_f, &acc_data, 0);
        SetFibAccelerationData(V, macAdMask_userDefine_f, &acc_data, 1);
    }

    if ((DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_STATIC)) && (!DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC)))
    {
        SetFibAccelerationData(V, macAd_isStatic_f, &acc_data, 1);
        SetFibAccelerationData(V, macAdMask_isStatic_f, &acc_data, 1);
    }

    if ((DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC)) && (!DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_STATIC)))
    {
        SetFibAccelerationData(V, macAd_isStatic_f, &acc_data, 0);
        SetFibAccelerationData(V, macAdMask_isStatic_f, &acc_data, 1);
    }

    if ((DRV_ACC_OP_BY_MAC != (in->op_type&DRV_ACC_OP_BY_MAC)) && (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_UCAST)) && (!DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_MCAST)))
    {
        SetFibAccelerationData(A, macKey_mappedMac_f, &acc_data, hw_mac_mask);
        hw_mac_mask[1] = 1 << 8;  /* mappedMac(40) */
        SetFibAccelerationData(A, macKeyMask_mappedMac_f, &acc_data, hw_mac_mask);
    }

    if ((DRV_ACC_OP_BY_MAC != (in->op_type&DRV_ACC_OP_BY_MAC)) && (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_MCAST)) && (!DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_UCAST)))
    {
        hw_mac_mask[1] = 1 << 8;  /* mappedMac(40) */
        SetFibAccelerationData(A, macKey_mappedMac_f, &acc_data, hw_mac_mask);
        SetFibAccelerationData(A, macKeyMask_mappedMac_f, &acc_data, hw_mac_mask);
    }

    SetFibAccelerationData(V, macKey_pending_f, &acc_data, (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_PENDING))?1:0);
    SetFibAccelerationData(V, macKeyMask_pending_f, &acc_data, (in->type==DRV_ACC_TYPE_DUMP_FLEX || DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_PENDING))?1:0);

    DRV_APP_REG_IOW(lchip,FibAccelerationData_t,&acc_data,0);
    if(ret != 0) return ret;

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_MAC_FLUSH_DUMP_BY_FLEX);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, hw_mac);
    SetFibHashKeyCpuReq(V, cpuKeyDsAdIndex_f, cpu_req, in->query_cnt);
    SetFibHashKeyCpuReq(V, cpuKeyIndex_f, cpu_req, key_index);
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_flush(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    uint32 key_index = 0;
    uint32 del_type  = 0;
    uint32 del_mode  = 0;
    uint16 fid = 0;
    DsFibHost0MacHashKey_m* p_mac_key = NULL;
    hw_mac_addr_t   mac = {0};
    uint32 req_type = 0;

    if (in->op_type == DRV_ACC_OP_BY_ALL)
    {
       req_type = DRV_ACC_CHIP_MAC_FLUSH_DUMP_BY_ALL;
    }
    else if ((in->op_type == DRV_ACC_OP_BY_PORT) ||
       (in->op_type == DRV_ACC_OP_BY_VLAN) ||
       (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_VLAN)))
    {
       req_type = DRV_ACC_CHIP_MAC_FLUSH_BY_PORT_VLAN;

       if (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_VLAN))
        {    /*delete by port+vsi*/
            del_type = 0;
        }
        else if (in->op_type == DRV_ACC_OP_BY_PORT)
        {    /*delete by port*/
            del_type = 1;
        }
        else if (in->op_type == DRV_ACC_OP_BY_VLAN)
        {    /*delete by vsi*/
            del_type = 2;
        }
        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
         {
             /*logic port do not update port mac limit*/
             key_index &= ~(1<<5);
             del_mode = 1;
             key_index |= (1 << 3);
         }
    }
    else if ((in->op_type == DRV_ACC_OP_BY_MAC)||
       (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_MAC)))
    {
        req_type = DRV_ACC_CHIP_MAC_FLUSH_BY_MAC_PORT;
        if (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_MAC))
         {    /*delete by mac+port*/
             del_type = 2;
         }
         else
         {    /*delete by mac*/
             del_type = 1;
         }
        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
         {
             /*logic port do not update port mac limit*/
             key_index &= ~(1<<5);
             del_mode = 1;
         }
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_STATIC))
    {
        key_index |= 1;
    }
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC))
    {
        key_index |= 1 << 1;
    }
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_UPDATE_MAC_LIMIT_CNT))
    {
        key_index |= 1 << 5;
        key_index |= 1 << 7;
        key_index |= 1 << 11;
    }

    /*profile*/
    key_index |= 1 << 9;
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_STATIC_MAC_LIMIT_CNT))
    {
        key_index |= 1 << 4;
        key_index |= 1 << 6;
        key_index |= 1 << 8;
    }

    p_mac_key = (DsFibHost0MacHashKey_m*)in->data;
    fid = GetDsFibHost0MacHashKey(V, vsiId_f, p_mac_key);
    GetDsFibHost0MacHashKey(A, mappedMac_f, p_mac_key, mac);

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, req_type);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, mac);
    SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, cpu_req, fid);
    SetFibHashKeyCpuReq(V, cpuKeyDelType_f, cpu_req, del_type);
    SetFibHashKeyCpuReq(V, cpuKeyIndex_f, cpu_req, key_index);
    SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, cpu_req, del_mode);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqPort_f, cpu_req, in->gport);

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_flush_cache(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    uint16 fid = 0;
    DsFibHost0MacHashKey_m* p_mac_key = NULL;
    hw_mac_addr_t   mac = {0};
    MacLearningCache_m learn_cache_mask;

    sal_memset(&learn_cache_mask, 0, sizeof(MacLearningCache_m));

    if (in->op_type & DRV_ACC_OP_BY_ALL)
    {
        /*do nothing*/
    }
    else
    {
        p_mac_key = (DsFibHost0MacHashKey_m *)in->data;
        fid = GetDsFibHost0MacHashKey(V, vsiId_f, p_mac_key);
        GetDsFibHost0MacHashKey(A, mappedMac_f, p_mac_key, mac);
        if (in->op_type & DRV_ACC_OP_BY_MAC || in->op_type & DRV_ACC_OP_BY_KEY)
        {
            SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, mac);
            mac[0] = 0xFFFFFFFF;
            mac[1] = 0xFFFF;
            SetMacLearningCache(A, mac_f, &learn_cache_mask, mac);
        }
        if (in->op_type & DRV_ACC_OP_BY_VLAN || in->op_type & DRV_ACC_OP_BY_KEY)
        {
            SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, cpu_req, fid);
            SetMacLearningCache(V, vsiId_f, &learn_cache_mask, 0xFFFF);
        }
        if (in->op_type & DRV_ACC_OP_BY_PORT)
        {
            SetFibHashKeyCpuReq(V, hashKeyCpuReqPort_f, cpu_req, in->gport);
            SetMacLearningCache(V, port_f, &learn_cache_mask, 0xFFFF);
            if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
            {
                SetFibHashKeyCpuReq(V, staticCountEn_f, cpu_req, 0);
            }
            else
            {
                SetFibHashKeyCpuReq(V, staticCountEn_f, cpu_req, 1);
            }
            SetMacLearningCache(V, isGlobalPort_f, &learn_cache_mask, 1);
        }
    }

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_MAC_FLUSH_CACHE);
    SetFibHashKeyCpuReq(A, writeData_f, cpu_req, &learn_cache_mask);
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_write_mac_by_key(uint8 lchip,drv_acc_in_t* acc_in, uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    out->key_index = GetFibHashKeyCpuResult(V, hashCpuLuIndex_f, fib_acc_cpu_rlt);
    out->is_full   = GetFibHashKeyCpuResult(V, pending_f, fib_acc_cpu_rlt);
    out->is_conflict  = GetFibHashKeyCpuResult(V, conflict_f, fib_acc_cpu_rlt);

#if (SDB_DISABLE != SDB_MODE)
    if(DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_FORCE_STORE_SDB))
    {
        uint8 enable = 0;
        uint8* p_sdb_data;

        drv_sdb_get_table_enable(lchip, acc_in->tbl_id, &enable);
        if(0 == enable)
        {
            return DRV_E_NONE;
        }
        if(out->key_index >= DRV_CONST(DRV_FIB_HOST0_CAM_NUM))
        {
            DRV_MCHIP_SDB_API(lchip)->drv_sdb_write_api(lchip, acc_in->tbl_id, out->key_index - DRV_CONST(DRV_FIB_HOST0_CAM_NUM), 
                                                     acc_in->data, DYNAMIC_TABLE_UNIT_SIZE(lchip, acc_in->tbl_id), acc_in->oper_bmp);
        }
        else
        {
            p_sdb_data = (uint8*)drv_sdb_read(lchip, DsFibHost0HashMacCam_t, out->key_index>>2, TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t), acc_in->oper_bmp);
            sal_memcpy(p_sdb_data+((out->key_index&0x3)*TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t)>>2), acc_in->data, (TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t)>>2));
            DRV_MCHIP_SDB_API(lchip)->drv_sdb_write_api(lchip, DsFibHost0HashMacCam_t, out->key_index>>2, p_sdb_data, 
                                                     TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t), acc_in->oper_bmp);
        }
    }
#endif

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_del_mac_by_key(uint8 lchip, drv_acc_in_t* acc_in,uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    out->key_index = GetFibHashKeyCpuResult(V, hashCpuLuIndex_f, fib_acc_cpu_rlt);
    out->is_hit       = GetFibHashKeyCpuResult(V, hashCpuKeyHit_f, fib_acc_cpu_rlt);
    out->is_conflict  = GetFibHashKeyCpuResult(V, conflict_f, fib_acc_cpu_rlt);
#if (SDB_DISABLE != SDB_MODE)
    if(DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_FORCE_STORE_SDB))
    {
        uint8 enable = 0;
        uint8* p_sdb_data;

        drv_sdb_get_table_enable(lchip, acc_in->tbl_id, &enable);
        if(0 == enable)
        {
            return DRV_E_NONE;
        }
        if(out->key_index >= DRV_CONST(DRV_FIB_HOST0_CAM_NUM))
        {
            DRV_MCHIP_SDB_API(lchip)->drv_sdb_write_api(lchip, acc_in->tbl_id, out->key_index - DRV_CONST(DRV_FIB_HOST0_CAM_NUM), 
                                     acc_in->data, DYNAMIC_TABLE_UNIT_SIZE(lchip, acc_in->tbl_id), acc_in->oper_bmp);
        }
        else
        {
            p_sdb_data = (uint8*)drv_sdb_read(lchip, DsFibHost0HashMacCam_t, out->key_index>>2, TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t), acc_in->oper_bmp);
            sal_memcpy(p_sdb_data+((out->key_index&0x3)*TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t)>>2), acc_in->data, (TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t)>>2));
            DRV_MCHIP_SDB_API(lchip)->drv_sdb_write_api(lchip, DsFibHost0HashMacCam_t, out->key_index>>2, p_sdb_data, 
                                     TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t), acc_in->oper_bmp);
        }
    }
#endif
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_null(uint8 lchip,drv_acc_in_t* acc_in, uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_lkp_mac_by_key(uint8 lchip,drv_acc_in_t* acc_in, uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    out->is_hit       = GetFibHashKeyCpuResult(V, hashCpuKeyHit_f, fib_acc_cpu_rlt);
    out->key_index = GetFibHashKeyCpuResult(V, hashCpuLuIndex_f, fib_acc_cpu_rlt);
    out->is_conflict  = GetFibHashKeyCpuResult(V, hashCpuConflictValid_f, fib_acc_cpu_rlt);
    out->is_pending   = GetFibHashKeyCpuResult(V, pending_f, fib_acc_cpu_rlt);
    out->ad_index  = GetFibHashKeyCpuResult(V, hashCpuDsIndex_f, fib_acc_cpu_rlt);

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_dump_mac(uint8 lchip, drv_acc_in_t* acc_in,uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    uint32 confict = 0;
    uint32 pending = 0;

    confict = GetFibHashKeyCpuResult(V, conflict_f, fib_acc_cpu_rlt);
    pending = GetFibHashKeyCpuResult(V, pending_f, fib_acc_cpu_rlt);

    out->key_index = GetFibHashKeyCpuResult(V, hashCpuLuIndex_f, fib_acc_cpu_rlt);
    out->is_full   = (confict && (!pending));

    if (DRV_IS_DUET2(lchip))
    {
        out->is_end = confict && pending;
    }
    else
    {
        out->is_end = (out->key_index == ((uint32)TABLE_MAX_INDEX(lchip,  DsFibHost0MacHashKey_t) + 32 - 1));
    }

    out->query_cnt      = GetFibHashKeyCpuResult(V, hashCpuDsIndex_f, fib_acc_cpu_rlt);
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_flex(uint8 lchip, drv_acc_in_t* acc_in,uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    out->key_index = GetFibHashKeyCpuResult(V, hashCpuLuIndex_f, fib_acc_cpu_rlt);
    /**********
      conflict_f      pending_f
         0              0               exceed the max index of fdb table
         0              1               exceed user configured threshold
         1              0               only for dump fdb, means dma is full
         1              1               exceed the max index of fdb table
    *********/
    out->is_end = !(GetFibHashKeyCpuResult(V, conflict_f, fib_acc_cpu_rlt) ^ GetFibHashKeyCpuResult(V, pending_f, fib_acc_cpu_rlt));
    out->query_cnt      = GetFibHashKeyCpuResult(V, hashCpuDsIndex_f, fib_acc_cpu_rlt);
    out->is_full = (GetFibHashKeyCpuResult(V, conflict_f, fib_acc_cpu_rlt) && !GetFibHashKeyCpuResult(V, pending_f, fib_acc_cpu_rlt));
    return DRV_E_NONE;
}

#define __ACC_HOST0__

STATIC int32
_drv_usw_acc_prepare_write_fib0_by_key(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    hw_mac_addr_t          hw_mac     = { 0 };
/*#if (SDK_WORK_PLATFORM == 1)
    uint32                 key_length = 0;
    uint32                 tbl_id     = 0;
#endif*/
    uint32                 length = 0;
    uint32                 overwrite_en = 0;
    uint8                  hash_type = 0;
    DsFibHost0FcoeHashKey_m* p_host0_key = NULL;

    p_host0_key = (DsFibHost0FcoeHashKey_m*)in->data;
    hash_type = GetDsFibHost0FcoeHashKey(V, hashType_f, p_host0_key);

    hw_mac[0] = hash_type;

    if ((in->tbl_id == DsFibHost0FcoeHashKey_t) || (in->tbl_id == DsFibHost0Ipv4HashKey_t)
        || (in->tbl_id == DsFibHost0MacHashKey_t) || (in->tbl_id == DsFibHost0TrillHashKey_t))
    {
        hw_mac[0] |= HASH_KEY_LENGTH_MODE_SINGLE << 3;
/*#if (SDK_WORK_PLATFORM == 1)
        key_length = DRV_HASH_85BIT_KEY_LENGTH;
        tbl_id     = DsFibHost0MacHashKey_t;
#endif*/
        length     = DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE);
    }
    else
    {
        hw_mac[0] |= HASH_KEY_LENGTH_MODE_DOUBLE << 3;
/*#if (SDK_WORK_PLATFORM == 1)
        key_length = DRV_HASH_170BIT_KEY_LENGTH;
        tbl_id     = DsFibHost0MacIpv6McastHashKey_t;
#endif*/
        length     = DRV_CONST(DRV_HOST0_DOUBLE_KEY_BYTE);
    }

    overwrite_en = DRV_IS_BIT_SET(in->flag, DRV_ACC_OVERWRITE_EN);

    sal_memcpy((uint8*)cpu_req, (uint8 *)in->data, length);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_HOST0_WRITE_BY_KEY);
    SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, cpu_req, overwrite_en);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, hw_mac);
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_lkp_fib0_by_idx(uint8 lchip, drv_acc_in_t* in, uint32* cpu_req)
{
    uint32        length_mode= 0;
    uint32        count      = 0;
    hw_mac_addr_t hw_mac     = { 0 };

    if (DRV_IS_DUET2(lchip))
    {
        hw_mac[0] = in->index - (in->index  & 3);
        count     = (in->index  & 3) >> 1;
    }
    else
    {
        hw_mac[0] = in->index ;
    }

    if ((in->tbl_id == DsFibHost0FcoeHashKey_t) || (in->tbl_id == DsFibHost0Ipv4HashKey_t)
        || (in->tbl_id == DsFibHost0MacHashKey_t) || (in->tbl_id == DsFibHost0TrillHashKey_t))
    {
        length_mode = HASH_KEY_LENGTH_MODE_SINGLE;
    }
    else
    {
        length_mode = HASH_KEY_LENGTH_MODE_DOUBLE;
    }

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_HOST0_lOOKUP_BY_INDEX);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, hw_mac);

    /* only cmodel need spec and rtl do not need */
    if (1 == count)
    {
        SetFibHashKeyCpuReq(V, staticCountEn_f, cpu_req, length_mode);
    }
    else
    {
        SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, cpu_req, length_mode);
    }

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_write_fib0_by_idx(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    drv_fib_acc_rw_data_t tmp_rw_data;
    drv_acc_in_t      acc_read_in;
    drv_acc_out_t     acc_read_out;
#if (SDK_WORK_PLATFORM == 1)
    uint32                count      = 0;
    uint32                key_length_mode[2] = { 0 };
#endif
    uint32                key_index  = 0;
    uint8                 shift      = 0;
    hw_mac_addr_t         hw_mac = { 0 };
    FibHashKeyCpuReq_m fib_req;
    FibHashKeyCpuResult_m fib_result;
    sal_memset(&tmp_rw_data, 0, sizeof(drv_fib_acc_rw_data_t));
    sal_memset(&acc_read_in, 0, sizeof(drv_acc_in_t));
    sal_memset(&acc_read_out, 0, sizeof(drv_acc_out_t));

    hw_mac[0] = in->index - (in->index & 3);

#if (SDK_WORK_PLATFORM == 1)
    count     = (in->index  & 3)  >> 1;

    if ((in->tbl_id == DsFibHost0FcoeHashKey_t) || (in->tbl_id == DsFibHost0Ipv4HashKey_t)
        || (in->tbl_id == DsFibHost0MacHashKey_t) || (in->tbl_id == DsFibHost0TrillHashKey_t))
    {
        key_length_mode[count] = HASH_KEY_LENGTH_MODE_SINGLE;
    }
    else
    {
        key_length_mode[count] = HASH_KEY_LENGTH_MODE_DOUBLE;
    }
#endif

    key_index = in->index - (in->index & 3);

    /* read by index, for 340bits */
    acc_read_in.type = DRV_ACC_TYPE_LOOKUP;
    acc_read_in.op_type = DRV_ACC_OP_BY_INDEX;
    acc_read_in.index = key_index;
    acc_read_in.tbl_id = DsFibHost0HashCam_t;
    /*Note: can not using drv_acc_host0 directly, because of lock, using internal interface*/
    DRV_IF_ERROR_RETURN(drv_usw_acc_host0_prepare(lchip, &acc_read_in, (uint32*)&fib_req));
    DRV_IF_ERROR_RETURN(drv_usw_acc_host0_process(lchip, (uint32*)&fib_req, (uint32*)&fib_result,0, 0));
    DRV_IF_ERROR_RETURN(drv_usw_acc_host0_result(lchip, &acc_read_in, (uint32*)&fib_result, &acc_read_out));

    /* move request data to read data */
    shift = (in->index & 3);
    sal_memcpy(tmp_rw_data, acc_read_out.data, sizeof(tmp_rw_data));
    sal_memcpy(((uint32 *) tmp_rw_data + shift * 3), in->data, TABLE_ENTRY_SIZE(lchip, in->tbl_id));

    sal_memcpy((uint8*)cpu_req, (uint8 *)tmp_rw_data, DRV_CONST(DRV_HOST0_QUAD_KEY_BYTE));
    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_HOST0_WRITE_BY_INDEX);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, hw_mac);

#if (SDK_WORK_PLATFORM == 1)
    /* only cmodel need spec and rtl do not need */
    SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, cpu_req, key_length_mode[0]);
    SetFibHashKeyCpuReq(V, staticCountEn_f, cpu_req, key_length_mode[1]);
#endif
    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_lkp_fib0_by_key(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    hw_mac_addr_t          hw_mac     = { 0 };
    uint8                  hash_type = 0;
    DsFibHost0FcoeHashKey_m* p_host0_key = NULL;
    uint16    key_size = 0;

    p_host0_key = (DsFibHost0FcoeHashKey_m*)in->data;
    hash_type = GetDsFibHost0FcoeHashKey(V, hashType_f, p_host0_key);

    hw_mac[0] = hash_type;
    if ((in->tbl_id == DsFibHost0FcoeHashKey_t) || (in->tbl_id == DsFibHost0Ipv4HashKey_t)
        || (in->tbl_id == DsFibHost0MacHashKey_t) || (in->tbl_id == DsFibHost0TrillHashKey_t))
    {
        hw_mac[0] |= HASH_KEY_LENGTH_MODE_SINGLE << 3;
        key_size  = DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE);
    }
    else
    {
        hw_mac[0] |= HASH_KEY_LENGTH_MODE_DOUBLE << 3;
        key_size  = DRV_CONST(DRV_HOST0_DOUBLE_KEY_BYTE);
    }

    sal_memcpy((uint8*)cpu_req, (uint8 *)in->data, key_size);

    SetDsFibHost0FcoeHashKey(V, dsAdIndex_f, (DsFibHost0FcoeHashKey_m*)cpu_req, 0);

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, cpu_req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, cpu_req, DRV_ACC_CHIP_HOST0_lOOKUP_BY_KEY);
    SetFibHashKeyCpuReq(A, cpuKeyMac_f, cpu_req, hw_mac);

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_write_fib0_by_key(uint8 lchip, uint32* cpu_rlt, drv_acc_out_t* out)
{
    out->key_index = GetFibHashKeyCpuResult(V, hashCpuLuIndex_f, cpu_rlt);
    out->is_conflict  = GetFibHashKeyCpuResult(V, conflict_f, cpu_rlt);
    out->ad_index = GetFibHashKeyCpuResult(V, hashCpuDsIndex_f, cpu_rlt);
    out->is_hit       = GetFibHashKeyCpuResult(V, hashCpuKeyHit_f, cpu_rlt);

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_lkp_fib0_by_idx(uint8 lchip, drv_acc_in_t* acc_in, uint32* cpu_rlt, drv_acc_out_t* out)
{
    uint8         shift = 0;
    drv_fib_acc_rw_data_t tmp_rw_data;

    sal_memset(&tmp_rw_data, 0, sizeof(tmp_rw_data));

    if (DRV_IS_DUET2(lchip))
    {
        sal_memcpy((uint8*)tmp_rw_data, (uint8 *)cpu_rlt, DRV_CONST(DRV_HOST0_QUAD_KEY_BYTE));

        /* asic only read 340 key drv need to adjust the key */
        if (acc_in->index < DRV_CONST(DRV_FIB_HOST0_CAM_NUM))
        {
            shift = (acc_in->index  & 3);
        }
        else
        {
            shift = ((acc_in->index - DRV_CONST(DRV_FIB_HOST0_CAM_NUM))  & 3);
        }
        sal_memcpy(out->data, ((uint32 *) tmp_rw_data + shift * 3), TABLE_ENTRY_SIZE(lchip,acc_in->tbl_id));
    }
    else
    {
        GetFibHashKeyCpuResult(A, readData_f, cpu_rlt, out->data);
    }

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_result_lkp_fib0_by_key(uint8 lchip, drv_acc_in_t* acc_in, uint32* cpu_rlt, drv_acc_out_t* out)
{
    out->is_hit       = GetFibHashKeyCpuResult(V, hashCpuKeyHit_f, cpu_rlt);
    out->key_index = GetFibHashKeyCpuResult(V, hashCpuLuIndex_f, cpu_rlt);
    out->is_conflict  = GetFibHashKeyCpuResult(V, hashCpuConflictValid_f, cpu_rlt);
    out->ad_index  = GetFibHashKeyCpuResult(V, hashCpuDsIndex_f, cpu_rlt);
    return DRV_E_NONE;
}

int32
drv_usw_acc_host0_prepare(uint8 lchip, drv_acc_in_t* acc_in, uint32* req)
{
    switch(acc_in->type)
    {
        case DRV_ACC_TYPE_ADD:
            if (acc_in->op_type == DRV_ACC_OP_BY_INDEX)
            {

                DRV_IF_ERROR_RETURN(_drv_usw_acc_prepare_write_fib0_by_idx(lchip,  acc_in, req));
            }
            else
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_prepare_write_fib0_by_key(lchip,  acc_in, req));
            }
            break;
         case DRV_ACC_TYPE_LOOKUP:
            if (acc_in->op_type == DRV_ACC_OP_BY_INDEX)
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_prepare_lkp_fib0_by_idx(lchip,  acc_in, req));
             }
            else
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_prepare_lkp_fib0_by_key(lchip,  acc_in, req));
            }
            break;
        default:
            return DRV_E_INVAILD_TYPE;

    }

    return 0;
}

int32
drv_usw_acc_host0_process(uint8 lchip, uint32* i_cpu_req, uint32* o_cpu_rlt,uint8 sleep_en, uint8 oper_bmp)
{
    uint16         loop  = 0;
    uint8         done  = 0;
    int32          ret   = 0;

#if(SDK_WORK_PLATFORM == 0)
    uint32        req_val = 0;
#else
   FibHashKeyCpuReq_m fib_req;
#endif



   DRV_APP_REG_IOW(lchip,FibHashKeyCpuReq_t,i_cpu_req,oper_bmp);
#if(SDK_WORK_PLATFORM == 0)
        DRV_ENTRY_LOCK(lchip);
#endif
    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && !done; loop++)
    {
#if(SDK_WORK_PLATFORM == 1)
        extern int32 sys_usw_chip_check_active(uint8 lchip);
        if ((ret = sys_usw_chip_check_active(lchip)) < 0)
        {
            return ret;
        }
#endif

#if(SDK_WORK_PLATFORM == 0)
           p_drv_master[lchip]->drv_chip_read(DRV_MAP_LDEV(lchip), DRV_ADDR_CORE_EN(DRV_CONST(DRV_ACCREQ_ADDR_HOST0)),1, &req_val);
           done = !(req_val & (1 << DRV_CONST(DRV_ACCREQ_BITOFFSET_HOST0)));
#else
{
          DRV_APP_REG_IOR(lchip,FibHashKeyCpuReq_t,i_cpu_req, DRV_ACC_PP_EN);
          if (DRV_FROM_AT(lchip) && (g_drv_vchip_mode || (drv_vchip_get_pp_num(lchip) > p_drv_master[lchip]->core_pp_num)))
          {
            DRV_APP_REG_IOR(4,FibHashKeyCpuReq_t,(void*)(&fib_req),DRV_ACC_PP_EN);/* PP_TODO */
            done = !GetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, i_cpu_req) && !GetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, (&fib_req));
          }
          else
          {
            done = !GetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, i_cpu_req);
          }
}
#endif
       if (done)
        {
            break;
        }
        if(sleep_en)
        {
#ifndef PACKET_TX_USE_SPINLOCK
            sal_task_sleep(1);
#else
            sal_udelay(1000);
#endif
        }
        DRV_ACC_WAIT_SLEEP
    }
#if(SDK_WORK_PLATFORM == 0)
       DRV_ENTRY_UNLOCK(lchip);
#endif

    if (!done)
    {
        return DRV_E_TIME_OUT;
    }
    DRV_APP_REG_IOR(lchip,FibHashKeyCpuResult_t,o_cpu_rlt,DRV_ACC_PP_EN);

    return ret;
}


int32
drv_usw_acc_host0_result(uint8 lchip, drv_acc_in_t* acc_in, uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    switch(acc_in->type)
    {
        case DRV_ACC_TYPE_ADD:

            if (acc_in->op_type != DRV_ACC_OP_BY_INDEX)
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_result_write_fib0_by_key(lchip, fib_acc_cpu_rlt, out));
            }

            break;
        case DRV_ACC_TYPE_DEL:
            break;

         case DRV_ACC_TYPE_LOOKUP:

            if (acc_in->op_type == DRV_ACC_OP_BY_INDEX)
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_result_lkp_fib0_by_idx(lchip, acc_in, fib_acc_cpu_rlt, out));
            }
            else if (acc_in->op_type == DRV_ACC_OP_BY_KEY)
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_result_lkp_fib0_by_key(lchip,acc_in,fib_acc_cpu_rlt, out));
            }
            break;

        default:
            return DRV_E_INVAILD_TYPE;

    }

    return 0;
}

STATIC INLINE int32
_drv_usw_acc_get_hash_type_by_tbl_id(uint8 lchip, uint32 tbl_id, uint32* p_hash_type, uint32* p_hash)
{
   uint32 out = 0;

   switch(tbl_id)
   {
   case DsFibHost0FcoeHashKey_t:
       out  =  DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_FCOE);
       break;

   case DsFibHost0Ipv4HashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV4);
       SetDsFibHost0Ipv4HashKey(V, pointer_f, p_hash, 0);
       break;

   case DsFibHost0Ipv6McastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6MCAST);
       SetDsFibHost0Ipv6McastHashKey(V, pointer_f, p_hash, 0);
       break;

   case DsFibHost0Ipv6UcastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6UCAST);
       break;

   case DsFibHost0MacIpv6McastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MACIPV6MCAST);
       SetDsFibHost0MacIpv6McastHashKey(V, pointer_f, p_hash, 0);
       break;

   case DsFibHost0TrillHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_TRILL);
       break;

   default:
       return DRV_E_INVAILD_TYPE;
   }

    *p_hash_type = out;

    return 0;
}
STATIC uint8
_drv_usw_acc_get_host1_hash_type(uint8 lchip, drv_acc_in_t* in);

STATIC int32
_drv_usw_acc_prepare_fib_hash_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    FibHashCpuLookupReq_m host1_req;
    FibHashCpuLookupResult_m host1_result;
    int32 ret = 0;
    uint8 length = 0;
    uint32 mode = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint8 req_interface = 0;
    uint32 hash_type = 0;
    DsFibHost1Ipv4McastHashKey_m* p_hash = NULL;
 #if(SDK_WORK_PLATFORM == 0)
    uint32     req_val = 0;
 #endif

    sal_memset(&host1_req, 0, sizeof(host1_req));
    /*for action by key, need do lookup first*/
    pre_info->tbl_id = in->tbl_id;

    length  = TABLE_ENTRY_SIZE(lchip, in->tbl_id);

    sal_memcpy((uint8*)&host1_req, (uint8 *)in->data, length);
    p_hash = (DsFibHost1Ipv4McastHashKey_m*)&host1_req;
    mode = (length == SINGLE_KEY_BYTE) ? HASH_KEY_LENGTH_MODE_SINGLE:
          ((length == DOUBLE_KEY_BYTE)?HASH_KEY_LENGTH_MODE_DOUBLE:HASH_KEY_LENGTH_MODE_QUAD);

    if (pre_info->hash_type == DRV_ACC_HASH_MODULE_FIB_HOST0)
    {
        req_interface = 2;
        _drv_usw_acc_get_hash_type_by_tbl_id(lchip, in->tbl_id, &hash_type, (uint32*)p_hash);
        SetFibHashCpuLookupReq(V, hashKeyType_f, &host1_req, hash_type);

        if (length == DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE))
        {
            SetDsFibHost0Ipv4HashKey(V, valid_f, p_hash, 1);

        }
        else if(length == DRV_CONST(DRV_HOST0_DOUBLE_KEY_BYTE))
        {
            SetDsFibHost0Ipv6UcastHashKey(V, valid0_f, p_hash, 1);
            SetDsFibHost0Ipv6UcastHashKey(V, valid1_f, p_hash, 1);
        }

        /*Clear adindex*/
        SetDsFibHost0Ipv4HashKey(V, dsAdIndex_f, p_hash, 0);

    }
    else if(pre_info->hash_type == DRV_ACC_HASH_MODULE_FLOW)
    {
        req_interface = 1;
        SetDsFlowL2HashKey(V, dsAdIndex_f, p_hash, 0);
    }
    else /*fib host 1*/
    {
        req_interface = 0;
        SetFibHashCpuLookupReq(V, hashKeyType_f, &host1_req, (_drv_usw_acc_get_host1_hash_type(lchip, in)));

        /*Clear adindex*/
        SetDsFibHost1Ipv4McastHashKey(V, dsAdIndex_f, p_hash, 0);
    }
    SetFibHashCpuLookupReq(V, cpuLookupReqValid_f, &host1_req, 1);
    SetFibHashCpuLookupReq(V, lengthMode_f, &host1_req, mode);
    SetFibHashCpuLookupReq(V, reqInterface_f, &host1_req, req_interface);

     DRV_APP_REG_IOW(lchip,FibHashCpuLookupReq_t,(uint32*)&host1_req, in->oper_bmp);
#if(SDK_WORK_PLATFORM == 0)
     DRV_ENTRY_LOCK(lchip);
#endif

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
#if(SDK_WORK_PLATFORM == 0)
         if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
         {
            not_done = 0;
            break;
         }
         p_drv_master[lchip]->drv_chip_read(DRV_MAP_LDEV(lchip),  DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_FIB)),1, &req_val);
          not_done = (req_val & (1 << DRV_CONST(DRV_ACCREQ_BITOFFSET_FIB)));
#else
        DRV_APP_REG_IOR(lchip, FibHashCpuLookupReq_t, &host1_req, DRV_ACC_PP_EN);
        not_done = GetFibHashCpuLookupReq(V, cpuLookupReqValid_f, &host1_req);
#endif
       if (!not_done)
        {
            break;
        }
       DRV_ACC_WAIT_SLEEP;
    }
#if(SDK_WORK_PLATFORM == 0)
        DRV_ENTRY_UNLOCK(lchip);
#endif
    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,FibHashCpuLookupResult_t,(uint32*)&host1_result,DRV_ACC_PP_EN);
    pre_info->conflict = GetFibHashCpuLookupResult(V, conflict_f, &host1_result);
    pre_info->valid = GetFibHashCpuLookupResult(V, lookupResultValid_f, &host1_result);
    /*acording lookup result build prepare information*/
    if (!GetFibHashCpuLookupResult(V, conflict_f, &host1_result))
    {
        pre_info->key_index = GetFibHashCpuLookupResult(V, resultIndex_f, &host1_result);
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;
    return ret;
}


#define __ACC_HOST1__
STATIC INLINE uint8
_drv_usw_acc_get_host1_hash_type(uint8 lchip, drv_acc_in_t* in)
{
    uint8 hash_type = 0;
    switch(in->tbl_id)
    {
        case DsFibHost1FcoeRpfHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_FCOERPF);
            break;
        case DsFibHost1Ipv4McastHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4MCAST);
            break;
        case DsFibHost1Ipv4NatDaPortHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATDAPORT);
            break;
        case DsFibHost1Ipv4NatSaPortHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATSAPORT);
            break;
        case DsFibHost1Ipv6McastHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6MCAST);
            break;
        case DsFibHost1Ipv6NatDaPortHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATDAPORT);
            break;
        case DsFibHost1Ipv6NatSaPortHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATSAPORT);
            break;
        case DsFibHost1MacIpv4McastHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV4MCAST);
            break;
        case DsFibHost1MacIpv6McastHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV6MCAST);
            break;
        case DsFibHost1TrillMcastVlanHashKey_t:
            hash_type =  DRV_CONST(DRV_FIBHOST1HASHTYPE_TRILLMCASTVLAN);
            break;
        default:
            break;
    }

    return hash_type;
}
int32
_drv_usw_acc_prepare_host1_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    FibHost1FlowHashCpuLookupReq_m host1_req;
    FibHost1FlowHashCpuLookupResult_m host1_result;
    int32 ret = 0;
    uint32 tbl_id = 0;
    uint8  length = 0;
    uint32 mode = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[12] = { 0 };
    DsFibHost1Ipv4McastHashKey_m* p_hash = NULL;
/*#if (SDK_WORK_PLATFORM == 1)
    uint8 c_length = 0;
#endif*/

    /* check valid bit clear */
    sal_memset(&host1_req, 0, sizeof(FibHost1FlowHashCpuLookupReq_m));

    /*for action by key, need do lookup first*/
    pre_info->tbl_id = in->tbl_id;
    tbl_id = in->tbl_id;

     length  = TABLE_ENTRY_SIZE(lchip, tbl_id);
     mode = (length == SINGLE_KEY_BYTE) ? HASH_KEY_LENGTH_MODE_SINGLE:
          ((length == DOUBLE_KEY_BYTE)?HASH_KEY_LENGTH_MODE_DOUBLE:HASH_KEY_LENGTH_MODE_QUAD);

    sal_memcpy((uint8*)data, (uint8 *)in->data, length);
    p_hash = (DsFibHost1Ipv4McastHashKey_m*)data;
    SetDsFibHost1Ipv4McastHashKey(V, dsAdIndex_f, p_hash, 0);

    sal_memcpy((uint8*)&host1_req, (uint8 *)data, length);
    SetFibHost1FlowHashCpuLookupReq(V, cpuLookupReqValid_f, &host1_req, 1);
    SetFibHost1FlowHashCpuLookupReq(V, lengthMode_f, &host1_req, mode);
    SetFibHost1FlowHashCpuLookupReq(V, fibHost1Req_f, &host1_req, 1);
    SetFibHost1FlowHashCpuLookupReq(V, fibHost1HashType_f, &host1_req, (_drv_usw_acc_get_host1_hash_type(lchip, in)));
    DRV_APP_REG_IOW(lchip,FibHost1FlowHashCpuLookupReq_t,&host1_req,0);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
        DRV_APP_REG_IOR(lchip,FibHost1FlowHashCpuLookupReq_t,&host1_req,0);
        not_done = GetFibHost1FlowHashCpuLookupReq(V, cpuLookupReqValid_f, &host1_req);
        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
       return DRV_E_CMD_NOT_DONE;
    }

    DRV_APP_REG_IOR(lchip,FibHost1FlowHashCpuLookupResult_t,&host1_result,0);
    pre_info->conflict = GetFibHost1FlowHashCpuLookupResult(V, conflict_f, &host1_result);
    pre_info->valid = GetFibHost1FlowHashCpuLookupResult(V, lookupResultValid_f, &host1_result);

    /*acording lookup result build prepare information*/
    if (!GetFibHost1FlowHashCpuLookupResult(V, conflict_f, &host1_result))
    {
        pre_info->tbl_id = tbl_id;
        pre_info->key_index = GetFibHost1FlowHashCpuLookupResult(V, resultIndex_f, &host1_result);
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;
    return ret;
}

#define __ACC_USERID__
STATIC int32
_drv_usw_acc_prepare_userid_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    UserIdCpuLookupReq_m userid_req;
    UserIdCpuLookupResult_m userid_result;
    int32  ret = 0;
    uint8  length= 0;
    uint32 mode = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[12] = { 0 };
    DsUserIdCvlanPortHashKey_m* p_hash = NULL;
#if(SDK_WORK_PLATFORM == 0)
    uint32   req_val = 0;
#endif

    sal_memset(&userid_req, 0, sizeof(UserIdCpuLookupReq_m));
    /*for action by key, need do lookup first*/
    length  = TABLE_ENTRY_SIZE(lchip, in->tbl_id);
    mode = (length == SINGLE_KEY_BYTE) ? HASH_KEY_LENGTH_MODE_SINGLE:
           ((length == DOUBLE_KEY_BYTE)?HASH_KEY_LENGTH_MODE_DOUBLE:HASH_KEY_LENGTH_MODE_QUAD);

    sal_memcpy((uint8*)data, (uint8 *)in->data, length);


    p_hash = (DsUserIdCvlanPortHashKey_m*)data;
    SetDsUserIdCvlanPortHashKey(V, dsAdIndex_f, p_hash, 0);

    if (p_drv_master[lchip]->dev_type != DRV_DUET2  && (in->level == 1))
    {
        SetUserIdCpuLookupReq(V, requestInterface_f, &userid_req, 1);
    }
    sal_memcpy((uint8*)&userid_req, (uint8 *)data, length);

    SetUserIdCpuLookupReq(V, cpuLookupReqValid_f, &userid_req, 1);
    SetUserIdCpuLookupReq(V, lengthMode_f, &userid_req, mode);
    DRV_APP_REG_IOW(lchip,UserIdCpuLookupReq_t,&userid_req,DRV_ACC_PP_EN);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
#if(SDK_WORK_PLATFORM == 0)
          DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_USERID)), &req_val));
          not_done = (req_val & (1 << DRV_CONST(DRV_ACCREQ_BITOFFSET_USERID)));
#else
          DRV_APP_REG_IOR(lchip, UserIdCpuLookupReq_t, &userid_req, DRV_ACC_PP_EN);
          not_done = GetUserIdCpuLookupReq(V, cpuLookupReqValid_f, &userid_req);
#endif
        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,UserIdCpuLookupResult_t,&userid_result,DRV_ACC_PP_EN);

    pre_info->conflict = GetUserIdCpuLookupResult(V, conflict_f, &userid_result);
    pre_info->valid = GetUserIdCpuLookupResult(V, lookupResultValid_f, &userid_result);

    /*acording lookup result build prepare information*/
    if (!GetUserIdCpuLookupResult(V, conflict_f, &userid_result))
    {
        pre_info->key_index = GetUserIdCpuLookupResult(V, resultIndex_f, &userid_result);
    }
   pre_info->is_cam = pre_info->key_index < pre_info->cam_num;
#if 0
    DRV_DBG_OUT("=============================\n");
    DRV_DBG_OUT("UserID Lookup keyinex:%d\n", pre_info->key_index);
    DRV_DBG_OUT("conflict:%d\n", pre_info->conflict);
    DRV_DBG_OUT("valid:%d\n", pre_info->valid);
#endif

    return ret;
}

#define __ACC_XCOAM__

STATIC int32
_drv_usw_acc_prepare_xcoam_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    EgressXcOamCpuLookupReq_m xcoam_req;
    EgressXcOamCpuLookupResult_m xcoam_result;
    int32 ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[12] = { 0 };
#if(SDK_WORK_PLATFORM == 0)
    uint32        req_val = 0;
#endif

    sal_memset(&xcoam_req, 0, sizeof(EgressXcOamCpuLookupReq_m));

    /*for action by key, need do lookup first*/
    pre_info->tbl_id = in->tbl_id;

#if (SDK_WORK_PLATFORM == 1)
{
    uint8 length = 0;
    length = TABLE_ENTRY_SIZE(lchip, in->tbl_id) - TABLE_ENTRY_SIZE(lchip, in->tbl_id) / 12;
    drv_model_hash_combined_key((uint8 *)data, (uint8 *)in->data, length, in->tbl_id);
    drv_model_hash_mask_key((uint8 *)data, (uint8 *)data, HASH_MODULE_EGRESS_SCL0, in->tbl_id);
}
#else
     sal_memcpy((uint8*)data, (uint8 *)in->data, TABLE_ENTRY_SIZE(lchip, in->tbl_id) );
    if ((DsEgressXcOamBfdHashKey_t == in->tbl_id)||(DsEgressXcOamEthHashKey_t == in->tbl_id)||(DsEgressXcOamMplsLabelHashKey_t == in->tbl_id)||
      (DsEgressXcOamMplsSectionHashKey_t == in->tbl_id)||(DsEgressXcOamRmepHashKey_t == in->tbl_id))
    {
        /*For oam hash key mask ad info*/
        *((uint32*)data+0) &= 0xffffffff;
        *((uint32*)data+1) &= 0x3ffff;
        *((uint32*)data+2) &= 0;
    }
#endif

    SetEgressXcOamCpuLookupReq(V, cpuLookupReqValid_f, &xcoam_req, 1);
    SetEgressXcOamCpuLookupReq(A, data_f, &xcoam_req, data);


    DRV_APP_REG_IOW(lchip,EgressXcOamCpuLookupReq_t,&xcoam_req,DRV_ACC_PP_EN);
    if(ret !=0) return ret;

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
#if(SDK_WORK_PLATFORM == 0)
          DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_CONST(DRV_ACCREQ_ADDR_EGRESSXCOAM), &req_val));
          not_done = (req_val & 1); /* DRV_CONST(DRV_ACCREQ_BITOFFSET_EGRESSXCOAM) is 0 */
#else
          DRV_APP_REG_IOR(lchip,EgressXcOamCpuLookupReq_t,&xcoam_req,DRV_ACC_PP_EN);
          not_done = GetEgressXcOamCpuLookupReq(V, cpuLookupReqValid_f, &xcoam_req);
#endif

        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,EgressXcOamCpuLookupResult_t,&xcoam_result,DRV_ACC_PP_EN);
    pre_info->conflict = GetEgressXcOamCpuLookupResult(V, conflict_f, &xcoam_result);
    pre_info->valid = GetEgressXcOamCpuLookupResult(V, lookupResultValid_f, &xcoam_result);

    /*acording lookup result build prepare information*/
    if (!GetEgressXcOamCpuLookupResult(V, conflict_f, &xcoam_result))
    {
        pre_info->key_index = GetEgressXcOamCpuLookupResult(V, resultIndex_f, &xcoam_result);
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;
    return ret;
}

#define __ACC_EGRESS_SCL__

STATIC int32
_drv_usw_acc_prepare_egress_scl_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    EgressSclCpuLookupReq_m egress_scl_req;
    EgressSclCpuLookupResult_m egress_scl_result;
    int32  ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[12] = { 0 };
    uint8 length = SINGLE_KEY_BYTE;

#if(SDK_WORK_PLATFORM == 0)
    uint32 req_val = 0;
#endif

    sal_memset(&egress_scl_req, 0, sizeof(EgressSclCpuLookupReq_m));
    /*for action by key, need do lookup first*/
    sal_memcpy((uint8*)data, (uint8 *)in->data, length);
    /*mask ad info*/
    sal_memset(&data[3], 0, sizeof(DsVlanXlate_m));
    sal_memcpy((uint8*)&egress_scl_req, (uint8 *)data, length);
    SetEgressSclCpuLookupReq(V, cpuLookupReqValid_f, &egress_scl_req, 1);
    DRV_APP_REG_IOW(lchip,EgressSclCpuLookupReq_t,&egress_scl_req,DRV_ACC_PP_EN);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
#if(SDK_WORK_PLATFORM == 0)
           DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_EGRESSSCL)), &req_val));
           not_done = (req_val & 1); /* DRV_ACCREQ_BITOFFSET_EGRESSSCL is 0 */
#else
          DRV_APP_REG_IOR(lchip, EgressSclCpuLookupReq_t, &egress_scl_req, DRV_ACC_PP_EN);
          not_done = GetEgressSclCpuLookupReq(V, cpuLookupReqValid_f, &egress_scl_req);
#endif

        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,EgressSclCpuLookupResult_t,&egress_scl_result,DRV_ACC_PP_EN);
    if (in->level)
    {
        pre_info->conflict = GetEgressSclCpuLookupResult(V, conflict1_f, &egress_scl_result);
        pre_info->valid = GetEgressSclCpuLookupResult(V, lookupResultValid1_f, &egress_scl_result);

        /*acording lookup result build prepare information*/
        if (!GetEgressSclCpuLookupResult(V, conflict1_f, &egress_scl_result))
        {
            pre_info->key_index = GetEgressSclCpuLookupResult(V, resultIndex1_f, &egress_scl_result);
        }
        pre_info->tcam_hit = GetEgressSclCpuLookupResult(V, isTcamHit1_f, &egress_scl_result);
    }
    else
    {
        pre_info->conflict = GetEgressSclCpuLookupResult(V, conflict0_f, &egress_scl_result);
        pre_info->valid = GetEgressSclCpuLookupResult(V, lookupResultValid0_f, &egress_scl_result);

        /*acording lookup result build prepare information*/
        if (!GetEgressSclCpuLookupResult(V, conflict0_f, &egress_scl_result))
        {
            pre_info->key_index = GetEgressSclCpuLookupResult(V, resultIndex0_f, &egress_scl_result);
        }
        pre_info->tcam_hit = GetEgressSclCpuLookupResult(V, isTcamHit0_f, &egress_scl_result);
    }
   pre_info->is_cam = pre_info->key_index < pre_info->cam_num;

 #if 0
    DRV_DBG_OUT("=============================\n");
    DRV_DBG_OUT("EgressScl Lookup keyinex:%d\n", pre_info->key_index);
    DRV_DBG_OUT("conflict:%d\n", pre_info->conflict);
    DRV_DBG_OUT("valid:%d\n", pre_info->valid);
#endif

    return ret;
}

#define __ACC_OAM__
STATIC int32
_drv_usw_acc_prepare_oam_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    OamCpuLookupReq_m oam_req;
    OamCpuLookupResult_m oam_result;
    int32  ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[12] = { 0 };


#if(SDK_WORK_PLATFORM == 0)
    uint32 req_val = 0;
#endif
    sal_memset(&oam_req, 0, sizeof(OamCpuLookupReq_m));

    /*for action by key, need do lookup first*/
    pre_info->tbl_id = in->tbl_id;

    sal_memcpy((uint8*)data, (uint8 *)in->data, TABLE_ENTRY_SIZE(lchip, in->tbl_id));
     /*For oam hash key mask ad info*/
    *((uint32*)data+0) &= 0xffffffff;
    *((uint32*)data+1) &= 0x1ffff;
    *((uint32*)data+2) &= 0;

    SetOamCpuLookupReq(V, cpuLookupReqValid_f, &oam_req, 1);
    SetOamCpuLookupReq(A, data_f, &oam_req, data);
    DRV_APP_REG_IOW(lchip,OamCpuLookupReq_t,&oam_req,DRV_ACC_PP_EN);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
#ifdef WARMBOOT
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
#endif
#if(SDK_WORK_PLATFORM == 0)
         DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_OAM)), &req_val));
         not_done = (req_val & 1); /* DRV_CONST(DRV_ACCREQ_BITOFFSET_OAM) is 0 */
#else
        DRV_APP_REG_IOR(lchip,OamCpuLookupReq_t,&oam_req,DRV_ACC_PP_EN);
        not_done = GetOamCpuLookupReq(V, cpuLookupReqValid_f, &oam_req);
#endif
        if (!not_done)
        {
            break;
        }
       DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,OamCpuLookupResult_t,&oam_result,DRV_ACC_PP_EN);
    pre_info->conflict = GetOamCpuLookupResult(V, conflict_f, &oam_result);
    pre_info->valid = GetOamCpuLookupResult(V, lookupResultValid_f, &oam_result);

    /*acording lookup result build prepare information*/
    if (!GetOamCpuLookupResult(V, conflict_f, &oam_result))
    {
        pre_info->key_index = GetOamCpuLookupResult(V, resultIndex_f, &oam_result);
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;
    return ret;
}

#define __ACC_RMEP__
STATIC int32
_drv_usw_acc_prepare_rmep_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    OamRmepCpuLookupReq_m rmep_req;
    OamRmepCpuLookupResult_m rmep_result;
    int32 ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[12] = { 0 };
#if(SDK_WORK_PLATFORM == 0)
    uint32        req_val = 0;
#endif
   uint8 entry_size = 0;
   uint8 length = 0;

    sal_memset(&rmep_req, 0, sizeof(OamRmepCpuLookupReq_m));

    /*for action by key, need do lookup first*/
    pre_info->tbl_id = in->tbl_id;
    entry_size  = TABLE_ENTRY_SIZE(lchip, in->tbl_id) / 8;
    switch (entry_size)
    {
        case 1:
            length   = SINGLE_KEY_BYTE;
            break;

        case 2:
            length   = DOUBLE_KEY_BYTE;
            break;

        case 4:
            length   = QUAD_KEY_BYTE;
            break;
        default:
            return DRV_E_INVALID_TBL;
    }

    sal_memcpy((uint8*)data, (uint8 *)in->data, length);
        /*For oam hash key mask ad info*/
        *((uint32*)data+0) &= 0xffffffff;
        *((uint32*)data+1) &= 0x1ffff;
        *((uint32*)data+2) &= 0;

    SetOamRmepCpuLookupReq(V, cpuLookupReqValid_f, &rmep_req, 1);
    SetOamRmepCpuLookupReq(A, data_f, &rmep_req, data);
    DRV_APP_REG_IOW(lchip,OamRmepCpuLookupReq_t,&rmep_req,DRV_ACC_PP_EN);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }

#if(SDK_WORK_PLATFORM == 0)
            DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_CONST(DRV_ACCREQ_ADDR_OAMRMEP), &req_val));
            not_done = (req_val & 1);  /* DRV_CONST(DRV_ACCREQ_BITOFFSET_OAMRMEP) is 0 */
#else
            DRV_APP_REG_IOR(lchip,OamRmepCpuLookupReq_t,&rmep_req,DRV_ACC_PP_EN);
            not_done = GetOamRmepCpuLookupReq(V, cpuLookupReqValid_f, &rmep_req);

#endif

        if (!not_done)
        {
            break;
        }
      DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,OamRmepCpuLookupResult_t,&rmep_result,DRV_ACC_PP_EN);
    pre_info->conflict = GetOamRmepCpuLookupResult(V, conflict_f, &rmep_result);
    pre_info->valid = GetOamRmepCpuLookupResult(V, lookupResultValid_f, &rmep_result);

    /*acording lookup result build prepare information*/
    if (!GetOamRmepCpuLookupResult(V, conflict_f, &rmep_result))
    {
        pre_info->key_index = GetOamRmepCpuLookupResult(V, resultIndex_f, &rmep_result);
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;
    return ret;
}

#define __ACC_QUEUE_MAP__

STATIC int32
_drv_usw_acc_prepare_queue_map_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    QueueHashCpuLookupReq_m queue_map_req;
    QueueHashCpuLookupResult_m queue_map_result;
    int32   ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[12] = { 0 };

    sal_memset(&queue_map_req, 0, sizeof(QueueHashCpuLookupReq_m));

    /*for action by key, need do lookup first*/
    sal_memcpy((uint8*)data, (uint8 *)in->data, TABLE_ENTRY_SIZE(lchip, in->tbl_id));
    SetDsQueueMapHashKey(V, queueBase_f, data, 0);
    SetDsQueueMapHashKey(V, queueOffsetMode_f, data, 0);
    SetQueueHashCpuLookupReq(A, data_f, &queue_map_req, data);
    DRV_APP_REG_IOW(lchip,QueueHashCpuLookupReq_t,&queue_map_req,0);
	SetQueueHashCpuLookupReq(V, lookupValid_f, &queue_map_req, 1);
    DRV_APP_REG_IOW(lchip,QueueHashCpuLookupReq_t,&queue_map_req,0);
    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
#ifdef WARMBOOT
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
#endif
        DRV_APP_REG_IOR(lchip,QueueHashCpuLookupReq_t,&queue_map_req,0);
        not_done = GetQueueHashCpuLookupReq(V, lookupValid_f, &queue_map_req);
        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,QueueHashCpuLookupResult_t,&queue_map_result,0);
    pre_info->conflict = GetQueueHashCpuLookupResult(V, conflict_f, &queue_map_result);
    pre_info->valid = GetQueueHashCpuLookupResult(V, lookupResultValid_f, &queue_map_result);

    /*acording lookup result build prepare information*/
    if (!GetQueueHashCpuLookupResult(V, conflict_f, &queue_map_result))
    {
        pre_info->tbl_id = in->tbl_id;
        pre_info->key_index = GetQueueHashCpuLookupResult(V, resultIndex_f, &queue_map_result);
    }
     pre_info->is_cam  = pre_info->key_index >= TABLE_MAX_INDEX(lchip, DsQueueMapHashKey_t);

#if 0
    DRV_DBG_OUT("=============================\n");
    DRV_DBG_OUT("Queue Map Lookup keyinex:%d\n", pre_info->key_index);
    DRV_DBG_OUT("conflict:%d\n", pre_info->conflict);
    DRV_DBG_OUT("valid:%d\n", pre_info->valid);
#endif
    return ret;
}


#define __ACC_FLOW__

STATIC int32
_drv_usw_acc_prepare_flow_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    FibHost1FlowHashCpuLookupReq_m flow_req;
    /*- FlowHashCpuLookupReq1_m flow_req1;*/
    FibHost1FlowHashCpuLookupResult_m flow_result;
    int32  ret = 0;
    uint8  length = 0;
    uint32 mode = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[12] = { 0 };
    DsFlowL2HashKey_m* p_l2hash = NULL;
/*#if (SDK_WORK_PLATFORM == 1)
    uint8 c_length = 0;
#endif*/

    /* check valid bit clear */
    sal_memset(&flow_req, 0, sizeof(FibHost1FlowHashCpuLookupReq_m));

    /*for action by key, need do lookup first*/
    pre_info->tbl_id = in->tbl_id;
    length  = TABLE_ENTRY_SIZE(lchip, in->tbl_id);
    mode = (length == SINGLE_KEY_BYTE) ? HASH_KEY_LENGTH_MODE_SINGLE:
          ((length == DOUBLE_KEY_BYTE)?HASH_KEY_LENGTH_MODE_DOUBLE:HASH_KEY_LENGTH_MODE_QUAD);

    sal_memcpy((uint8*)data, (uint8 *)in->data, length);
    p_l2hash = (DsFlowL2HashKey_m*)data;
    SetDsFlowL2HashKey(V, dsAdIndex_f, p_l2hash, 0);
    sal_memcpy((uint8*)&flow_req, (uint8 *)data, length);

    SetFibHost1FlowHashCpuLookupReq(V, cpuLookupReqValid_f, &flow_req, 1);
    SetFibHost1FlowHashCpuLookupReq(V, lengthMode_f, &flow_req, mode);
    SetFibHost1FlowHashCpuLookupReq(V, fibHost1Req_f, &flow_req, 0);
    DRV_APP_REG_IOW(lchip,FibHost1FlowHashCpuLookupReq_t,&flow_req,0);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
        DRV_APP_REG_IOR(lchip,FibHost1FlowHashCpuLookupReq_t,&flow_req,0);
        not_done = GetFibHost1FlowHashCpuLookupReq(V, cpuLookupReqValid_f, &flow_req);
        if (!not_done)
        {
            break;
        }
         DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }

    DRV_APP_REG_IOR(lchip,FibHost1FlowHashCpuLookupResult_t,&flow_result,0);
    pre_info->conflict = GetFibHost1FlowHashCpuLookupResult(V, conflict_f, &flow_result);
    pre_info->valid = GetFibHost1FlowHashCpuLookupResult(V, lookupResultValid_f, &flow_result);

    /*acording lookup result build prepare information*/
    if (!GetFibHost1FlowHashCpuLookupResult(V, conflict_f, &flow_result))
    {
        pre_info->key_index = GetFibHost1FlowHashCpuLookupResult(V, resultIndex_f, &flow_result);
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;
    return ret;
}

int32
drv_usw_acc_hash_process(uint8 lchip, drv_cpu_acc_prepare_info_t* p_info)
{
    uint32 index   = 0;
    uint32 step     = 0;
    uint32 cam_key[16] = { 0 };
    int32   ret = 0;
    uint8 sigle_sz = (p_info->hash_type == DRV_ACC_HASH_MODULE_FIB_HOST0) ? DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE) :
                     ((p_info->hash_type == DRV_ACC_HASH_MODULE_DOT1AE) ? DRV_CONST(DRV_DOT1AE_SINGLE_KEY_BYTE):SINGLE_KEY_BYTE);

    if (p_info->is_cam)
    {
        if (DsQueueMapHashCam_t == p_info->cam_table)
        {
            index = (p_info->key_index - TABLE_MAX_INDEX(lchip, DsQueueMapHashKey_t)) / p_info->cam_step;
            step  = (p_info->key_index - TABLE_MAX_INDEX(lchip, DsQueueMapHashKey_t)) % p_info->cam_step;
        }
        else
        {
            index = p_info->key_index / p_info->cam_step;
            step  = p_info->key_index % p_info->cam_step;
        }
#if (SDB_DISABLE != SDB_MODE && SDK_WORK_PLATFORM == 0)
        if (DRV_READ_MEM_FROM_SER(p_info->cam_table))
        {
            sal_memcpy(cam_key, (uint8*)drv_sdb_read(lchip, p_info->cam_table, index, TABLE_ENTRY_SIZE(lchip, p_info->cam_table), p_info->oper_bmp), TABLE_ENTRY_SIZE(lchip, p_info->cam_table));
        }
        else
#endif
		DRV_APP_TBL_IOR(lchip,p_info->cam_table,index,cam_key,p_info->oper_bmp);
        if (!p_info->is_read)
        {
            if (p_info->hash_type == DRV_ACC_HASH_MODULE_RMEP)
            {
                sal_memcpy(&(cam_key[ step <<1]), p_info->data, TABLE_ENTRY_SIZE(lchip, p_info->tbl_id));
            }
            else
            {
                sal_memcpy(&(cam_key[(sigle_sz >>2) * step]), p_info->data, TABLE_ENTRY_SIZE(lchip, p_info->tbl_id));
            }
             DRV_APP_TBL_IOW(lchip,p_info->cam_table,index,cam_key,p_info->oper_bmp);
        }
        else
        {
            if (p_info->hash_type == DRV_ACC_HASH_MODULE_RMEP)
            {
                sal_memcpy(p_info->data, &(cam_key[ step <<1]), TABLE_ENTRY_SIZE(lchip, p_info->tbl_id));
            }
            else
            {
                sal_memcpy(p_info->data, &(cam_key[(sigle_sz >>2) * step]), TABLE_ENTRY_SIZE(lchip, p_info->tbl_id));
            }
        }
    }
    else
    {
        if (DsQueueMapHashKey_t == p_info->tbl_id
            ||DsXSecRxL2BasicHashKey_t == p_info->tbl_id
            ||DsXSecRxL2MacsecHashKey_t == p_info->tbl_id
            ||DsXSecRxL3L4V4HashKey_t == p_info->tbl_id
            ||DsXSecRxL3L4V6HashKey_t == p_info->tbl_id
            ||DsXSecRxSpiHashKey_t == p_info->tbl_id
            ||DsXSecTxL2BasicHashKey_t == p_info->tbl_id
            ||DsXSecTxL3L4V4HashKey_t == p_info->tbl_id
            ||DsXSecTxL3L4V6HashKey_t == p_info->tbl_id
            ||DsXSecTxSpiHashKey_t == p_info->tbl_id)
        {
            index = p_info->key_index;
        }
        else
        {
            index = (p_info->key_index - p_info->cam_num);
        }
        if (!p_info->is_read)
        {
            DRV_APP_TBL_IOW(lchip,p_info->tbl_id,index,p_info->data,p_info->oper_bmp);
        }
        else
        {
#if (SDB_DISABLE != SDB_MODE && SDK_WORK_PLATFORM == 0)
            if (DRV_READ_MEM_FROM_SER(p_info->tbl_id))
            {
                sal_memcpy(p_info->data, (uint8*)drv_sdb_read(lchip, p_info->tbl_id, index, DYNAMIC_TABLE_UNIT_SIZE(lchip, p_info->tbl_id), p_info->oper_bmp), TABLE_ENTRY_SIZE(lchip, p_info->tbl_id));
                return ret;
            }
#endif
           DRV_APP_TBL_IOR(lchip,p_info->tbl_id,index,p_info->data,p_info->oper_bmp);
        }
    }

    return ret;
}

int32
drv_usw_acc_hash_result(uint8 lchip, drv_acc_in_t* acc_in, drv_cpu_acc_prepare_info_t* pre_info, drv_acc_out_t* out)
{
    out->is_conflict = pre_info->conflict;
    out->is_hit = pre_info->valid;
    out->key_index = pre_info->key_index;
    out->tcam_hit = pre_info->tcam_hit;
    if (pre_info->hash_type == DRV_ACC_HASH_MODULE_DOT1AE)
    {
        out->data[0]= pre_info->is_cam;
    }

    if (acc_in->op_type == DRV_ACC_OP_BY_INDEX)
    {
        sal_memcpy((uint8*)out->data, (uint8*)pre_info->data, TABLE_ENTRY_SIZE(lchip, pre_info->tbl_id));
    }
    else  if (acc_in->op_type == DRV_ACC_OP_BY_KEY
              && acc_in->type == DRV_ACC_TYPE_LOOKUP  &&  pre_info->hash_type == DRV_ACC_HASH_MODULE_FIB_HOST0)
    {
        out->ad_index =  GetDsFibHost0Ipv4HashKey(V, dsAdIndex_f, pre_info->data);
    }

    return 0;
}

#define __MAC_LIMIT__
STATIC int32
_drv_usw_acc_prepare_read_mac_limit(uint8 lchip, drv_acc_in_t* acc_in, uint32* req)
{
    uint32 mac_limit_type = 0;
    uint32 cpu_req_port = 0;
    uint32 index = 0;
    uint16 fid = 0;
    uint32 ipv6_high_bits[3] = {0};

    if (acc_in->op_type == DRV_ACC_OP_BY_PORT)
    {
        /*Get port base mac limit state*/
        if (DRV_GPORT_TO_GCHIP(acc_in->gport) == 0x1f)
        {
            index = DRV_GPORT_TO_LPORT(acc_in->gport);
        }
        else
        {
            index = DRV_FROM_TMM(lchip)? DRV_GPORT_TO_LPORT(acc_in->gport) + TABLE_MAX_INDEX(lchip, DsLinkAggregateGroup_t)
                                       : DRV_GPORT_TO_LPORT(acc_in->gport) + TABLE_MAX_INDEX(lchip, DsLinkAggregateGroup_t)/2;
        }

        mac_limit_type = 1;
        ipv6_high_bits[0] = acc_in->gport & 0xffff;
        ipv6_high_bits[1] = (1 << 20) ;
        SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, req, ipv6_high_bits);
    }
    else if (acc_in->op_type == DRV_ACC_OP_BY_VLAN)
    {
        DRV_PTR_VALID_CHECK(acc_in->data);
        fid = *(uint16*)(acc_in->data);

        /*Get vlan base mac limit state*/
        index = DRV_FROM_TMM(lchip)? TABLE_MAX_INDEX(lchip, DsLinkAggregateGroup_t) + 512 + fid
                                   : TABLE_MAX_INDEX(lchip, DsLinkAggregateGroup_t) / 2 + 256 + fid;
        mac_limit_type = 1;

        ipv6_high_bits[1] = fid & 0x7fff;
        ipv6_high_bits[1] |= (1 << 21);
        SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, req, ipv6_high_bits);
    }
    else if (acc_in->op_type == DRV_ACC_OP_BY_ALL)
    {
        if (DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_STATIC_MAC_LIMIT_CNT))
        {
            /*Get profile base mac limit state*/
            mac_limit_type = 3;
            ipv6_high_bits[1] = (1 << 24);
            SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, req, ipv6_high_bits);
        }
        else
        {
            /*Get dynamic base mac limit state*/
            mac_limit_type = 2;
             ipv6_high_bits[1] = (1 << 23);
            SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, req, ipv6_high_bits);
        }
    }

    if (mac_limit_type == 1)
    {
        cpu_req_port = (((index & 0x1f) << 8) | (index >> 5));
        SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, req, index);
        SetFibHashKeyCpuReq(V, hashKeyCpuReqPort_f, req, cpu_req_port);
    }

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, req, 1);
    SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, req, DRV_ACC_CHIP_LIMIT_READ);
    SetFibHashKeyCpuReq(V, cpuKeyDelType_f, req, mac_limit_type);

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_write_mac_limit(uint8 lchip, drv_acc_in_t* acc_in, uint32* req)
{
    uint32 index = 0;
    uint16 fid = 0;
    uint32 del_type = 0;
    hw_mac_addr_t hw_mac       = { 0 };
    uint32   cpu_req_port = 0;
    uint32 ipv6_high_bits[3] = {0};

    if (acc_in->op_type == DRV_ACC_OP_BY_PORT)
    {
        /*port base mac limit state*/
        if (DRV_GPORT_TO_GCHIP(acc_in->gport) == 0x1f)
        {
            index = DRV_GPORT_TO_LPORT(acc_in->gport);
        }
        else
        {
            index = DRV_FROM_TMM(lchip)? DRV_GPORT_TO_LPORT(acc_in->gport) + TABLE_MAX_INDEX(lchip, DsLinkAggregateGroup_t)
                                        : DRV_GPORT_TO_LPORT(acc_in->gport) + TABLE_MAX_INDEX(lchip, DsLinkAggregateGroup_t) / 2;

        }
        del_type = 1;
        SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, req, index);

        ipv6_high_bits[0] = acc_in->gport & 0xffff;
        ipv6_high_bits[1] = (1 << 20) | (acc_in->limit_cnt << 15);
        SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, req, ipv6_high_bits);
    }
    else if (acc_in->op_type == DRV_ACC_OP_BY_VLAN)
    {
        DRV_PTR_VALID_CHECK(acc_in->data);
        fid = *(uint16*)(acc_in->data);

        /*vlan base mac limit state*/
        index = DRV_FROM_TMM(lchip)? TABLE_MAX_INDEX(lchip, DsLinkAggregateGroup_t) + 512 + fid
                                        : TABLE_MAX_INDEX(lchip, DsLinkAggregateGroup_t)/2 + 256 + fid;
        del_type = 1;
        SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, req, index);

        ipv6_high_bits[1] = fid & 0x7fff;
        ipv6_high_bits[1] |= (1 << 21) | ( acc_in->limit_cnt<< 17);
        SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, req, ipv6_high_bits);

    }
    else if (acc_in->op_type == DRV_ACC_OP_BY_ALL)
    {
        if (DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_STATIC_MAC_LIMIT_CNT))
        {
            /*profile base mac limit state*/
            del_type = 3;

            ipv6_high_bits[1] = (1 << 24) | ( acc_in->limit_cnt<< 19);
            SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, req, ipv6_high_bits);
        }
        else
        {
            /*dynamic base mac limit state*/
            del_type = 2;

            ipv6_high_bits[1] = (1 << 23) | ( acc_in->limit_cnt<< 18);
            SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, req, ipv6_high_bits);
        }
    }

    if (!DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_OVERWRITE_EN))
    {
        /* update maclimit */
        cpu_req_port = (((index & 0x1f) << 8) | (index >> 5));
        if (DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_MAC_LIMIT_NEGATIVE))
        {
            cpu_req_port |= 1 <<13;
        }

        SetFibHashKeyCpuReq(V, hashKeyCpuReqPort_f, req, cpu_req_port);

        if (DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_MAC_LIMIT_STATUS))
        {
            SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, req, acc_in->limit_cnt);/* tm2 discard bit */
            hw_mac[0] = 1<<1;
        }
        else
        {
            SetFibHashKeyCpuReq(V, cpuKeyIndex_f, req, acc_in->limit_cnt);
            hw_mac[0] = 1;
        }

        SetFibHashKeyCpuReq(A, cpuKeyMac_f, req, hw_mac);
        SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, req, DRV_ACC_CHIP_LIMIT_UPDATE);
    }
    else
    {
        /* write maclimit */
        SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, req, DRV_ACC_CHIP_LIMIT_WRITE);
        SetFibHashKeyCpuReq(V, cpuKeyIndex_f, req, acc_in->limit_cnt);
    }

    SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, req, 1);
    SetFibHashKeyCpuReq(V, cpuKeyDelType_f, req, del_type);

    return DRV_E_NONE;
}

#define __ACC_IPFIX__

STATIC int32
_drv_usw_acc_prepare_write_ipfix(uint8 lchip, uint8 by_index, drv_acc_in_t* acc_in, uint32* req)
{

    uint8 is_340bits = 0;
    uint8 len = 0;
    len = TABLE_ENTRY_SIZE(lchip, acc_in->tbl_id);
    is_340bits = (len== QUAD_KEY_BYTE) ;

    SetIpfixHashAdCpuReq(V, cpuReqType_f, req, (by_index?DRV_IPFIX_REQ_WRITE_BY_IDX:DRV_IPFIX_REQ_WRITE_BY_KEY));
    SetIpfixHashAdCpuReq(V, cpuReqValid_f, req, 1);
    if(by_index)
    {
        SetIpfixHashAdCpuReq(V, u1_gWriteByIndex_cpuIndex_f, req, acc_in->index);
        SetIpfixHashAdCpuReq(V, u1_gWriteByIndex_dataType_f, req, is_340bits);
    }
    else
    {
        SetIpfixHashAdCpuReq(V, u1_gWriteByKey_dataType_f, req, is_340bits);
    }
    sal_memcpy((uint8*)req, (uint8 *)acc_in->data, len);

    if (acc_in->tbl_id == DsIpfixSessionRecord_t ||
        acc_in->tbl_id == DsIpfixSessionRecord0_t||
        acc_in->tbl_id == DsIpfixSessionRecord1_t)
    {
        /*write ad*/
        SetIpfixHashAdCpuReq(V, isAdMemOperation_f, req, 1);
    }
    else
    {
        SetIpfixHashAdCpuReq(V, isAdMemOperation_f, req, 0);
    }

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_del_ipfix(uint8 lchip, uint8 by_index, drv_acc_in_t* acc_in, uint32* req)
{
    uint8  is_340bits = 0;
    uint8 len = 0;

    if (0 == by_index)
    {
        return DRV_E_INVAILD_TYPE;
    }
   len = TABLE_ENTRY_SIZE(lchip, acc_in->tbl_id);
   is_340bits = (len== QUAD_KEY_BYTE) ;

    SetIpfixHashAdCpuReq(V, cpuReqType_f, req, DRV_IPFIX_REQ_WRITE_BY_IDX);
    SetIpfixHashAdCpuReq(V, cpuReqValid_f, req, 1);
    SetIpfixHashAdCpuReq(V, u1_gWriteByIndex_cpuIndex_f, req, acc_in->index);
    SetIpfixHashAdCpuReq(V, u1_gWriteByIndex_dataType_f, req, is_340bits);

    sal_memcpy((uint8*)req, (uint8 *)acc_in->data, len);

    if (acc_in->tbl_id == DsIpfixSessionRecord_t ||
        acc_in->tbl_id == DsIpfixSessionRecord0_t||
        acc_in->tbl_id == DsIpfixSessionRecord1_t)
    {
        /*write ad*/
        SetIpfixHashAdCpuReq(V, isAdMemOperation_f, req, 1);
    }
    else
    {
        SetIpfixHashAdCpuReq(V, isAdMemOperation_f, req, 0);
    }

    return DRV_E_NONE;
}

STATIC int32
_drv_usw_acc_prepare_lkp_ipfix(uint8 lchip, uint8 by_idx, drv_acc_in_t* acc_in, uint32* req)
{
    uint8  is_340bits = 0;
    uint8 len = 0;

   len = TABLE_ENTRY_SIZE(lchip, acc_in->tbl_id);
   is_340bits = (len== QUAD_KEY_BYTE) ;

    SetIpfixHashAdCpuReq(V, cpuReqValid_f, req, 1);
    if (!by_idx)
    {
        sal_memcpy((uint8*)req, (uint8 *)acc_in->data, len);
        SetIpfixHashAdCpuReq(V, cpuReqType_f, req, DRV_IPFIX_REQ_LKP_BY_KEY);
        SetIpfixHashAdCpuReq(V, u1_gLookupByKey_dataType_f, req, is_340bits);
    }
    else
    {
        SetIpfixHashAdCpuReq(V, cpuReqType_f, req, DRV_IPFIX_REQ_LKP_BY_IDX);
        SetIpfixHashAdCpuReq(V, u1_gReadByIndex_dataType_f, req, is_340bits);
        SetIpfixHashAdCpuReq(V, u1_gReadByIndex_cpuIndex_f, req, acc_in->index);
    }

    if (acc_in->tbl_id == DsIpfixSessionRecord_t ||
        acc_in->tbl_id == DsIpfixSessionRecord0_t||
        acc_in->tbl_id == DsIpfixSessionRecord1_t)
    {
        /*write ad*/
        SetIpfixHashAdCpuReq(V, isAdMemOperation_f, req, 1);
    }
    else
    {
        SetIpfixHashAdCpuReq(V, isAdMemOperation_f, req, 0);
    }

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_ipfix_data_combined(uint8 lchip, uint8 is_ad_mem, uint8 dir, void* data, uint8* data_combined)
{
    ds_t data_tmp;
    sal_memset(&data_tmp, 0, sizeof(ds_t));
    if ((is_ad_mem) && (0 == dir))
    {
        GetDsIpfixSessionRecordMem0(A, data_f, data, data_tmp);
        SetDsIpfixSessionRecordMem0Combined(A, data_f, data_combined, data_tmp);
    }
    else if ((is_ad_mem) && (1 == dir))
    {
        GetDsIpfixSessionRecordMem1(A, data_f, data, data_tmp);
        SetDsIpfixSessionRecordMem1Combined(A, data_f, data_combined, data_tmp);
    }
    else
    {
        SetDsIpfixHashKeyMemCombined(V, hashKeyType0_f, data_combined, GetDsIpfixHashKeyMem(V, hashKeyType0_f, data));
        SetDsIpfixHashKeyMemCombined(V, hashKeyType1_f, data_combined, GetDsIpfixHashKeyMem(V, hashKeyType1_f, data));
        SetDsIpfixHashKeyMemCombined(V, hashKeyType2_f, data_combined, GetDsIpfixHashKeyMem(V, hashKeyType2_f, data));
        SetDsIpfixHashKeyMemCombined(V, hashKeyType3_f, data_combined, GetDsIpfixHashKeyMem(V, hashKeyType3_f, data));
        GetDsIpfixHashKeyMem(A, data_f, data, data_tmp);
        SetDsIpfixHashKeyMemCombined(A, data_f, data_combined, data_tmp);
        if(DRV_FROM_AT(lchip))
        {
            SetDsIpfixHashKeyMemCombined(V, xKeyValid0_f, data_combined, GetDsIpfixHashKeyMem(V, xKeyValid0_f, data));
            SetDsIpfixHashKeyMemCombined(V, xKeyValid1_f, data_combined, GetDsIpfixHashKeyMem(V, xKeyValid1_f, data));
            SetDsIpfixHashKeyMemCombined(V, xKeyValid2_f, data_combined, GetDsIpfixHashKeyMem(V, xKeyValid2_f, data));
            SetDsIpfixHashKeyMemCombined(V, xKeyValid3_f, data_combined, GetDsIpfixHashKeyMem(V, xKeyValid3_f, data));
        }
    }
    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_ipfix_data_uncombined(uint8 lchip, uint8 is_ad_mem, uint8 dir, void* data_combined, uint8* data)
{

    ds_t data_tmp;
    sal_memset(&data_tmp, 0, sizeof(ds_t));

    if ((is_ad_mem) && (0 == dir))
    {
        GetDsIpfixSessionRecordMem0Combined(A, data_f, data_combined, data_tmp);
        SetDsIpfixSessionRecordMem0(A, data_f, data, data_tmp);

    }
    else if ((is_ad_mem) && (1 == dir))
    {
        GetDsIpfixSessionRecordMem1Combined(A, data_f, data_combined, data_tmp);
        SetDsIpfixSessionRecordMem1(A, data_f, data, data_tmp);
    }
    else
    {
        SetDsIpfixHashKeyMem(V, hashKeyType0_f, data, GetDsIpfixHashKeyMemCombined(V, hashKeyType0_f, data_combined));
        SetDsIpfixHashKeyMem(V, hashKeyType1_f, data, GetDsIpfixHashKeyMemCombined(V, hashKeyType1_f, data_combined));
        SetDsIpfixHashKeyMem(V, hashKeyType2_f, data, GetDsIpfixHashKeyMemCombined(V, hashKeyType2_f, data_combined));
        SetDsIpfixHashKeyMem(V, hashKeyType3_f, data, GetDsIpfixHashKeyMemCombined(V, hashKeyType3_f, data_combined));
        SetDsIpfixHashKeyMem(V, xKeyValid0_f, data, GetDsIpfixHashKeyMemCombined(V, xKeyValid0_f, data_combined));
        SetDsIpfixHashKeyMem(V, xKeyValid1_f, data, GetDsIpfixHashKeyMemCombined(V, xKeyValid1_f, data_combined));
        SetDsIpfixHashKeyMem(V, xKeyValid2_f, data, GetDsIpfixHashKeyMemCombined(V, xKeyValid2_f, data_combined));
        SetDsIpfixHashKeyMem(V, xKeyValid3_f, data, GetDsIpfixHashKeyMemCombined(V, xKeyValid3_f, data_combined));

        GetDsIpfixHashKeyMemCombined(A, data_f, data_combined, data_tmp);
        SetDsIpfixHashKeyMem(A, data_f, data, data_tmp);
    }
    return DRV_E_NONE;
}


STATIC int32
_drv_tmm_acc_prepare_write_ipfix(uint8 lchip, uint8 by_index, drv_acc_in_t* acc_in, uint32* req)
{
    uint8 bytes = 0;
    ds_t data;
    ds_t mask;
    ds_t data_combined;
    ds_t mask_combined;

    uint8 bytes_offset = 0;
    uint8 is_ad_mem = 0;
    uint8 ad_operate = 0;
    uint8 shift = 0;
    uint32 key_type = 0;
    uint32 cpuIndex = 0;
    uint8 is_delete = (DRV_ACC_TYPE_DEL == acc_in->type)?1:0;
    uint8 flow_entry_update_cnt = 0;

    if (is_delete && (0 == by_index))
    {
        return DRV_E_INVAILD_TYPE;
    }

    sal_memset(&data, 0, sizeof(ds_t));
    sal_memset(&mask, 0, sizeof(ds_t));
    sal_memset(&data_combined, 0, sizeof(ds_t));
    sal_memset(&mask_combined, 0, sizeof(ds_t));

    bytes = TABLE_ENTRY_SIZE(lchip, acc_in->tbl_id);

    if (acc_in->tbl_id == DsIpfixSessionFullRecord0_t ||
        acc_in->tbl_id == DsIpfixSessionFullRecord1_t ||
        acc_in->tbl_id == DsIpfixSessionHalfRecord0_t ||
        acc_in->tbl_id == DsIpfixSessionRecord0_t ||
        acc_in->tbl_id == DsIpfixSessionRecord1_t ||
        acc_in->tbl_id == DsIpfixSessionRecord_t ||
        acc_in->tbl_id == DsIpfixSessionHalfRecord1_t)
        {
            if (0 == by_index)
            {
                return DRV_E_INVAILD_TYPE;
            }
            is_ad_mem = 1;
            if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
            {
                DRV_BIT_SET(ad_operate, acc_in->dir);/* ingress or egress AD*/
            }
            else
            {
                if (acc_in->dir == 0)
                {
                    ad_operate|= 0x3;
                }
                else
                {
                    ad_operate|= 0x1;
                }
            }
        }

    SetIpfixHashAdCpuReq(V, cpuReqType_f, req, (by_index? DRV_IPFIX_REQ_WRITE_BY_IDX : DRV_IPFIX_REQ_WRITE_BY_KEY));
    SetIpfixHashAdCpuReq(V, cpuReqValid_f, req, 1);
    SetIpfixHashAdCpuReq(V, isAdMemOperation_f, req, is_ad_mem);

    flow_entry_update_cnt = acc_in->value;

    if(by_index)
    {
        if (is_ad_mem)
        {
            if (DRV_FROM_AT(lchip))
            {
                cpuIndex = acc_in->index + (ad_operate << 15);/*240bits*/
            }
            else
            {
                cpuIndex = (acc_in->index >> 1) + (ad_operate << 17);/*240bits*/
            }
        }
        else
        {
            cpuIndex = (acc_in->index >> 2);/*480bits*/
        }
        SetIpfixHashAdCpuReq(V, u1_gWriteByIndex_cpuIndex_f, req, cpuIndex);
        SetIpfixHashAdCpuReq(V, u1_gWriteByIndex_flowEntryUpdateType_f, req, is_delete?2:1);/*add*/
        SetIpfixHashAdCpuReq(V, u1_gWriteByIndex_flowEntryUpdateCnt_f, req, flow_entry_update_cnt);/*add one entry*/

        shift = (bytes / TABLE_ENTRY_SIZE(lchip, DsIpfixL3Ipv4ShortHashKey_t)) - 1;/*4W unit*/
        if (is_ad_mem && (DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            bytes_offset = bytes*((acc_in->index >> shift)&(0x1 >> shift));
            if (1 == acc_in->dir)
            {
                bytes_offset += TABLE_ENTRY_SIZE(lchip, DsIpfixSessionRecordMem0_t);
            }
        }
        else if(!is_ad_mem)
        {
            bytes_offset = bytes*((acc_in->index >> shift)&(0x3 >> shift));
        }

        if (is_delete)
        {
            sal_memset((uint8 *)data + bytes_offset, 0, bytes);
        }
        else
        {
            sal_memcpy((uint8 *)data + bytes_offset, (uint8 *)acc_in->data, bytes);
        }
        sal_memset((uint8 *)mask + bytes_offset, 0xFF, bytes);
        if (is_ad_mem && (DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            SetDsIpfixSessionHalfRecord0(V, flowChangeCnt_f, (uint8 *)mask + bytes_offset, 0);/*flowChangeCnt is in the same location for different AD*/
        }
        if (1 == acc_in->dir && (DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            uint8 egs_ad_offset = TABLE_ENTRY_SIZE(lchip, DsIpfixSessionFullRecord0_t);
            _drv_tmm_acc_ipfix_data_combined(lchip, is_ad_mem, acc_in->dir, (uint8*)data + egs_ad_offset, (uint8*)data_combined + egs_ad_offset);
            _drv_tmm_acc_ipfix_data_combined(lchip, is_ad_mem, acc_in->dir, (uint8*)mask + egs_ad_offset, (uint8*)mask_combined + egs_ad_offset);
        }
        else if((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)) || (DRV_FROM_AT(lchip)&&(!is_ad_mem)))
        {
            _drv_tmm_acc_ipfix_data_combined(lchip, is_ad_mem, acc_in->dir, data, (uint8*)data_combined);
            _drv_tmm_acc_ipfix_data_combined(lchip, is_ad_mem, acc_in->dir, mask, (uint8*)mask_combined);
        }
        else
        {
            sal_memcpy((uint8 *)data_combined, (uint8 *)data, bytes);
            sal_memcpy((uint8 *)mask_combined, (uint8 *)mask, bytes);
        }
        SetIpfixHashAdCpuReq(A, u1_gWriteByIndex_writeData_f, req, (uint8 *)data_combined);
        SetIpfixHashAdCpuReq(A, u1_gWriteByIndex_writeMask_f, req, (uint8 *)mask_combined);
    }
    else
    {
        uint32 key_size = 0;
        SetIpfixHashAdCpuReq(V, u1_gWriteByKey_isDeleteOperation_f, req, is_delete);
        SetIpfixHashAdCpuReq(V, u1_gWriteByKey_flowEntryUpdateCnt_f, req, flow_entry_update_cnt);
        key_size = bytes / TABLE_ENTRY_SIZE(lchip, DsIpfixL3Ipv4ShortHashKey_t);
        if (key_size == 4)
        {
            key_size = 3;
        }
        SetIpfixHashAdCpuReq(V, u1_gWriteByKey_keySize_f, req, key_size);
        key_type = GetDsIpfixL2HashKey(V, hashKeyType0_f, acc_in->data);
        SetIpfixHashAdCpuReq(V, u1_gWriteByKey_hashKeyType_f, req, key_type);
        sal_memcpy((uint8 *)data, (uint8 *)acc_in->data, bytes);
        _drv_tmm_acc_ipfix_data_combined(lchip, 0, acc_in->dir, data, (uint8*)data_combined);
        SetIpfixHashAdCpuReq(A, u1_gWriteByKey_writeData_f, req, (uint8 *)data_combined);
    }

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_prepare_lkp_ipfix(uint8 lchip, uint8 by_index, drv_acc_in_t* acc_in, uint32* req)
{
    uint8 bytes = 0;
    ds_t data;
    ds_t data_combined;
    uint8 is_ad_mem = 0;
    uint8 ad_operate = 0;
    uint32 key_type = 0;
    uint32 cpuIndex = 0;

    sal_memset(&data, 0, sizeof(ds_t));
    sal_memset(&data_combined, 0, sizeof(ds_t));
    bytes = TABLE_ENTRY_SIZE(lchip, acc_in->tbl_id);

    if (acc_in->tbl_id == DsIpfixSessionFullRecord0_t ||
        acc_in->tbl_id == DsIpfixSessionFullRecord1_t ||
        acc_in->tbl_id == DsIpfixSessionHalfRecord0_t ||
        acc_in->tbl_id == DsIpfixSessionHalfRecord1_t ||
        acc_in->tbl_id == DsIpfixSessionRecord_t      ||
        acc_in->tbl_id == DsIpfixSessionRecord0_t     ||
        acc_in->tbl_id == DsIpfixSessionRecord1_t)
        {
            if (0 == by_index)
            {
                return DRV_E_INVAILD_TYPE;
            }
            is_ad_mem = 1;
            if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
            {
                DRV_BIT_SET(ad_operate, acc_in->dir);/* ingress or egress AD*/
            }
            else
            {
                if (acc_in->dir == 0)
                {
                    ad_operate |= 0x3;
                }
                else
                {
                    ad_operate |= 0x1;
                }
            }
        }

    SetIpfixHashAdCpuReq(V, cpuReqType_f, req, (by_index? DRV_IPFIX_REQ_LKP_BY_IDX : DRV_IPFIX_REQ_LKP_BY_KEY));
    SetIpfixHashAdCpuReq(V, cpuReqValid_f, req, 1);
    SetIpfixHashAdCpuReq(V, isAdMemOperation_f, req, is_ad_mem);

    if(by_index)
    {
        if (is_ad_mem)
        {
            if(DRV_FROM_AT(lchip))
            {
              cpuIndex = acc_in->index + (ad_operate << 15);/*240bits*/
            }
            else
            {
              cpuIndex = (acc_in->index >>1)+ (ad_operate << 17);/*240bits*/
            }
        }
        else
        {
            cpuIndex = (acc_in->index >> 2);/*480bits*/
        }
        SetIpfixHashAdCpuReq(V, u1_gReadByIndex_cpuIndex_f, req, cpuIndex);
    }
    else
    {
        key_type = GetDsIpfixL2HashKey(V, hashKeyType0_f, acc_in->data);
        SetIpfixHashAdCpuReq(V, u1_gLookupByKey_hashKeyType_f, req, key_type);
        sal_memcpy((uint8 *)data, (uint8 *)acc_in->data, bytes);
        _drv_tmm_acc_ipfix_data_combined(lchip, 0, 0, data, (uint8*)data_combined);
       // SetIpfixHashAdCpuReq(A, u1_gLookupByKey_lookupKey_f, req, (uint8 *)data);
        SetIpfixHashAdCpuReq(A, u1_gLookupByKey_lookupKey_f, req, (uint8 *)data_combined);
    }

    return DRV_E_NONE;
}


int32
drv_usw_acc_ipfix_prepare(uint8 lchip, drv_acc_in_t* acc_in, uint32* req)
{
    switch (acc_in->type)
    {
        case DRV_ACC_TYPE_ADD:
            if (DRV_FROM_TMM(lchip))
            {
                DRV_IF_ERROR_RETURN(_drv_tmm_acc_prepare_write_ipfix(lchip, (acc_in->op_type == DRV_ACC_OP_BY_INDEX)? 1 : 0, acc_in, req));
            }
            else
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_prepare_write_ipfix(lchip, (acc_in->op_type == DRV_ACC_OP_BY_INDEX)? 1 : 0, acc_in, req));
            }
            break;

        case DRV_ACC_TYPE_LOOKUP:
            if (DRV_FROM_TMM(lchip))
            {
                DRV_IF_ERROR_RETURN(_drv_tmm_acc_prepare_lkp_ipfix(lchip, (acc_in->op_type == DRV_ACC_OP_BY_INDEX)? 1 : 0, acc_in, req));
            }
            else
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_prepare_lkp_ipfix(lchip, (acc_in->op_type == DRV_ACC_OP_BY_INDEX)? 1 : 0, acc_in, req));
            }
            break;

        case DRV_ACC_TYPE_DEL:
            if (DRV_FROM_TMM(lchip))
            {
                DRV_IF_ERROR_RETURN(_drv_tmm_acc_prepare_write_ipfix(lchip, (acc_in->op_type == DRV_ACC_OP_BY_INDEX)? 1 : 0, acc_in, req));
            }
            else
            {
                DRV_IF_ERROR_RETURN(_drv_usw_acc_prepare_del_ipfix(lchip, (acc_in->op_type == DRV_ACC_OP_BY_INDEX)? 1 : 0, acc_in, req));
            }
            break;
        default:
            return DRV_E_INVAILD_TYPE;

    }

    return 0;
}

int32
drv_usw_acc_ipfix_process(uint8 lchip, uint8 dir, void* i_ipfix_req, void* o_ipfix_result)
{

    uint32                      loop  = 0;
    uint32                     done  = 0;
    uint32                     req_tbl_id = 0;
    uint32                     rlt_tbl_id = 0;
    int32                      ret =0;

    if (DRV_IS_TSINGMA(lchip) || DRV_FROM_AT(lchip))
    {
        if (dir == 0)
        {
            req_tbl_id = IpfixHashAdCpuReq0_t;
            rlt_tbl_id = IpfixHashAdCpuResult0_t;
        }
        if (dir == 1)
        {
            req_tbl_id = IpfixHashAdCpuReq1_t;
            rlt_tbl_id = IpfixHashAdCpuResult1_t;
        }
    }
    else
    {
        req_tbl_id = IpfixHashAdCpuReq_t;
        rlt_tbl_id = IpfixHashAdCpuResult_t;
    }

    DRV_APP_REG_IOW(lchip, req_tbl_id, i_ipfix_req, DRV_ACC_PP_EN);
    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && !done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            done = 1;
            break;
        }
        DRV_APP_REG_IOR(lchip, req_tbl_id, i_ipfix_req, DRV_ACC_PP_EN);
        done = !GetIpfixHashAdCpuReq(V, cpuReqValid_f, i_ipfix_req);
        if(done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (!done)
    {
         return DRV_E_CMD_NOT_DONE;
    }

    DRV_APP_REG_IOR(lchip, rlt_tbl_id, o_ipfix_result, DRV_ACC_PP_EN);

    return ret;
}

int32
drv_usw_acc_ipfix_result(uint8 lchip, drv_acc_in_t* in, void* req_result, drv_acc_out_t* out)
{
    uint32                     ret_idx     = 0;
    uint32                     is_conflict = 0;
    uint32                     idx_invalid = 0;

    is_conflict = GetIpfixHashAdCpuResult(V, conflictValid_f, req_result);
    if(DRV_FROM_TMM(lchip))
    {
        idx_invalid = !(GetIpfixHashAdCpuResult(V, resultValid_f, req_result));
    }
    else
    {
        idx_invalid = GetIpfixHashAdCpuResult(V, invalidIndex_f, req_result);
    }
    ret_idx     = GetIpfixHashAdCpuResult(V, lookupReturnIndex_f, req_result);

    out->is_conflict = is_conflict;
    out->is_hit       = !idx_invalid;

    if (in->op_type == DRV_ACC_OP_BY_KEY)
    {
        out->key_index = ret_idx;
    }

    if ((in->op_type == DRV_ACC_OP_BY_INDEX)&&(DRV_FROM_TMM(lchip)))
    {
        out->is_hit = 1;
    }


    if (in->type == DRV_ACC_TYPE_LOOKUP && in->op_type == DRV_ACC_OP_BY_INDEX)
    {
        if (DRV_FROM_TMM(lchip))
        {
            uint8 is_ad_mem = 0;
            ds_t data;
            ds_t data_combined;
            uint8 bytes_offset = 0;
            uint8 shift = 0;
            uint8 bytes = TABLE_ENTRY_SIZE(lchip, in->tbl_id);
            sal_memset(&data, 0, sizeof(ds_t));
            sal_memset(&data_combined, 0, sizeof(ds_t));
            if (1 == in->dir&& (DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
            {
                bytes_offset = TABLE_ENTRY_SIZE(lchip, DsIpfixSessionFullRecord1_t);/*bytes of DsIpfixSessionFullRecord1_t*/
                sal_memcpy((uint8*)data_combined, (uint8 *)req_result + bytes_offset, TABLE_ENTRY_SIZE(lchip, DsIpfixL3Ipv6HashKey_t) - bytes_offset);
            }
            else
            {
                sal_memcpy((uint8*)data_combined, (uint8 *)req_result, (DRV_FROM_AT(lchip)?IPFIX_AT_COMBINE_SIZE:IPFIX_TMM_COMBINE_SIZE));
            }
            /* uncompress */
            if (in->tbl_id == DsIpfixSessionFullRecord0_t ||
               in->tbl_id == DsIpfixSessionFullRecord1_t ||
               in->tbl_id == DsIpfixSessionHalfRecord0_t ||
               in->tbl_id == DsIpfixSessionRecord0_t ||
               in->tbl_id == DsIpfixSessionRecord1_t ||
               in->tbl_id == DsIpfixSessionRecord_t ||
               in->tbl_id == DsIpfixSessionHalfRecord1_t)
            {
                is_ad_mem = 1;
            }
            if (is_ad_mem && DRV_FROM_AT(lchip))
            {
                 sal_memcpy((uint8*)out->data, (uint8 *)data_combined, bytes);
            }
            else
            {
                _drv_tmm_acc_ipfix_data_uncombined(lchip, is_ad_mem, in->dir, data_combined,  (uint8*)data);

                shift = (bytes / TABLE_ENTRY_SIZE(lchip, DsIpfixL3Ipv4ShortHashKey_t)) - 1;/*4W unit*/
                if (is_ad_mem)
                {
                    bytes_offset = bytes*((in->index >> shift)&(0x1 >> shift));
                }
                else
                {
                    bytes_offset = bytes*((in->index >> shift)&(0x3 >> shift));
                }
                sal_memcpy((uint8*)out->data, (uint8 *)data + bytes_offset, bytes);
            }
        }
        else
        {
            sal_memcpy((uint8*)out->data, (uint8 *)req_result, QUAD_KEY_BYTE);
        }
    }

    return DRV_E_NONE;
}

#define __ACC_DOT1AE
STATIC int32
_drv_usw_acc_prepare_dot1ae_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{

    int32  ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    ds_t ds_req;
    ds_t ds_result;
    uint32 req_tbl=0;
    uint32 result_tbl = 0;

#if(SDK_WORK_PLATFORM == 0)
    uint32 req_val = 0;
#endif

    sal_memset(&ds_req, 0, sizeof(ds_t));
    req_tbl = in->dir? XSecTxCpuLookupReq_t : XSecRxCpuLookupReq_t;
    result_tbl = in->dir? XSecTxCpuLookupResult_t : XSecRxCpuLookupResult_t;
    pre_info->cam_table = in->dir? DsXSecTxHashCam_t : DsXSecRxHashCam_t;
    g_drv_app_master[lchip].hash_info[DRV_ACC_HASH_MODULE_DOT1AE].cam_tbl_id = pre_info->cam_table;

    /*for action by key, need do lookup first*/
    pre_info->tbl_id = in->tbl_id;
    sal_memcpy((uint8*)ds_req, (uint8 *)in->data, TABLE_ENTRY_SIZE(lchip, in->tbl_id));

    //SetXSecCpuLookupReq(A, xSecData_f, &ds_req, data);
    SetXSecCpuLookupReq(V, cpuLookupReqValid_f, &ds_req, 1);
    SetXSecCpuLookupReq(V, keySize_f, &ds_req, in->value);

    DRV_APP_REG_IOW(lchip,req_tbl,&ds_req,in->oper_bmp);
	
    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
#ifdef WARMBOOT
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
#endif
#if(SDK_WORK_PLATFORM == 0)
         DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, in->dir?DRV_ADDR_DP_EN(DRV_CONST(DRV_ACCREQ_ADDR_DOT1AE_TX),in->dp_id):DRV_ADDR_DP_EN(DRV_CONST(DRV_ACCREQ_ADDR_DOT1AE_RX),in->dp_id), &req_val));
         not_done = (req_val & (1 << DRV_CONST(DRV_ACCREQ_BITOFFSET_DOT1AE)));
#else
        DRV_APP_REG_IOR(lchip,req_tbl,&ds_req,in->oper_bmp);
        not_done = GetXSecCpuLookupReq(V, cpuLookupReqValid_f, &ds_req);
#endif
        if (!not_done)
        {
            break;
        }
       DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
     {
         return DRV_E_CMD_NOT_DONE;
     }
     DRV_APP_REG_IOR(lchip,result_tbl,&ds_result,in->oper_bmp);
     pre_info->conflict = GetXSecCpuLookupResult(V, conflict_f, &ds_result);
     pre_info->valid = GetXSecCpuLookupResult(V, lookupResultValid_f, &ds_result);


    /*acording lookup result build prepare information*/
    if (!GetXSecCpuLookupResult(V, conflict_f, &ds_result))
    {
        pre_info->is_cam = GetXSecCpuLookupResult(V, isCam_f, &ds_result);
        pre_info->key_index = GetXSecCpuLookupResult(V, resultIndex_f, &ds_result);
    }
    return ret;
}

#define __ACC_CID__
int32
drv_usw_acc_cid_lookup(uint8 lchip, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    CidPairHashCpuLookupReq_m cid_req;
    CidPairHashCpuLookupResult_m cid_result;
    int32   ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint32 data[2] = {0};
    DsCategoryIdPairHashLeftKey_m cid_data;
    uint32 tbl_id = 0;
    uint32 src_cid = 0;
    uint32 dst_cid = 0;
    uint32 src_valid = 0;
    uint32 dst_valid = 0;
    uint32 entry_valid = 0;
#if(SDK_WORK_PLATFORM == 0)
    uint32 req_val = 0;
#endif
    sal_memset(&cid_req, 0, sizeof(CidPairHashCpuLookupReq_m));

    /*Data must using 1st array for acc interface, decode data using DsCategoryIdPairHashLeftKey*/
    /*Format is: SrcCid(8)+DstCid(8)+SrcValid(1)+DstValid(1)+EntryValid(1)*/
    src_cid = (GetDsCategoryIdPairHashLeftKey(V, array_0_srcCategoryId_f, (uint32*)acc_in->data));
    dst_cid = (GetDsCategoryIdPairHashLeftKey(V, array_0_destCategoryId_f, (uint32*)acc_in->data));
    src_valid = (GetDsCategoryIdPairHashLeftKey(V, array_0_srcCategoryIdClassfied_f, (uint32*)acc_in->data));
    dst_valid = (GetDsCategoryIdPairHashLeftKey(V, array_0_destCategoryIdClassfied_f, (uint32*)acc_in->data));
    entry_valid = (GetDsCategoryIdPairHashLeftKey(V, array_0_valid_f, (uint32*)acc_in->data));
    if (DRV_FROM_TMM(lchip))
    {
        data[0] = (((src_cid&0x1FFF) << 19) | (dst_cid << 3) | (src_valid << 2) | (dst_valid << 1) | entry_valid);
        data[1] = src_cid >> 13;
    }
    else
    {
        data[0] = ((src_cid << 11) | (dst_cid << 3) | (src_valid << 2) | (dst_valid << 1) | entry_valid);
    }

    SetCidPairHashCpuLookupReq(A, data_f, &cid_req, data);
    SetCidPairHashCpuLookupReq(V, cpuLookupReqValid_f, &cid_req, 1);
    DRV_APP_REG_IOW(lchip,CidPairHashCpuLookupReq_t,&cid_req,DRV_ACC_PP_EN);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
#if(SDK_WORK_PLATFORM == 0)
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
          DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_CIDPAIR)), &req_val));
           not_done = (req_val & (1 << DRV_CONST(DRV_ACCREQ_BITOFFSET_CIDPAIRHASH)));
#else
          DRV_APP_REG_IOR(lchip,CidPairHashCpuLookupReq_t,&cid_req,DRV_ACC_PP_EN);
          not_done = GetCidPairHashCpuLookupReq(V, cpuLookupReqValid_f, &cid_req);
 #endif
        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,CidPairHashCpuLookupResult_t,&cid_result,DRV_ACC_PP_EN);
    acc_out->is_conflict = !GetCidPairHashCpuLookupResult(V, hit_f, &cid_result) && !GetCidPairHashCpuLookupResult(V, freeValid_f, &cid_result);
    acc_out->is_hit = GetCidPairHashCpuLookupResult(V, hit_f, &cid_result);

    /*acording lookup result build prepare information*/
    if (!acc_out->is_conflict)
    {
        acc_out->is_left = GetCidPairHashCpuLookupResult(V, isLeft_f, &cid_result);
        acc_out->offset = GetCidPairHashCpuLookupResult(V, entryOffset_f, &cid_result);
        acc_out->key_index = GetCidPairHashCpuLookupResult(V, hashKeyIndex_f, &cid_result);

        tbl_id = acc_out->is_left?DsCategoryIdPairHashLeftKey_t:DsCategoryIdPairHashRightKey_t;
        DRV_APP_TBL_IOR(lchip,tbl_id,acc_out->key_index,&cid_data,DRV_ACC_PP_EN);
        if (! acc_out->offset)
         {
             acc_out->ad_index = (GetDsCategoryIdPairHashLeftKey(V, array_0_adIndex_f, &cid_data));
         }
         else
         {
             acc_out->ad_index = (GetDsCategoryIdPairHashLeftKey(V, array_1_adIndex_f, &cid_data));
         }
    }
    else
    {
        return DRV_E_NONE;
    }

    return ret;
}

#define __ACC_AGING__
int32
drv_usw_acc_aging(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    FibHashKeyCpuReq_m fib_req;
    FibHashKeyCpuResult_m fib_result;
    uint32 enable = 0;
    uint32 index = 0;
    int32 ret = 0;

   sal_memset(&fib_req, 0, sizeof(FibHashKeyCpuReq_m));
    FIB_ACC_LOCK(lchip);

     if(acc_in->data)
     {
         enable = *(uint8*)(acc_in->data);
     }

     index = (acc_in->index)&0x1FFFFF;

     if (DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_AGING_EN))
     {
         /*use aging ptr*/
         if (DRV_FROM_TMM(lchip))
         {
             index = (index | (1 << 21));
         }
         else
         {
             index = (index | (1 << 20));
         }
     }
     if (DRV_FROM_TMM(lchip))
     {
         SetFibHashKeyCpuReq(V, ponRuleType_f, &fib_req, acc_in->value);
     }
     SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, &fib_req, DRV_ACC_CHIP_WRITE_DSAGING);
     SetFibHashKeyCpuReq(V, cpuKeyIndex_f, &fib_req, index);
     SetFibHashKeyCpuReq(V, cpuKeyDelType_f, &fib_req, (acc_in->timer_index)&0x3);
     SetFibHashKeyCpuReq(V, staticCountEn_f, &fib_req, enable);
     SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, &fib_req, 1);
     SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, &fib_req, (acc_in->timer_index == 2)?0:1);
     ret = drv_usw_acc_host0_process(lchip, (uint32*)&fib_req, (uint32*)&fib_result,0, 0);
     FIB_ACC_UNLOCK(lchip);
     return ret;
}

int32
_drv_usw_acc_gemport_lookup(uint8 lchip, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    int32  ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    GemPortCpuLookupReq_m req;
    GemPortCpuLookupResult_m result;

    sal_memset(&req, 0, sizeof(req));

    SetGemPortCpuLookupReq(V, lookupValid_f, &req, 1);
    SetGemPortCpuLookupReq(A, data_f, &req, acc_in->data);
    DRV_APP_REG_IOW(lchip,GemPortCpuLookupReq_t,&req,DRV_ACC_PP_EN);
    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }

        DRV_APP_REG_IOR(lchip,GemPortCpuLookupReq_t,&req,DRV_ACC_PP_EN);
        not_done = GetGemPortCpuLookupReq(V, lookupValid_f, &req);
        if (!not_done)
        {
            break;
        }
       DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,GemPortCpuLookupResult_t,&result,DRV_ACC_PP_EN);
    acc_out->is_conflict = GetGemPortCpuLookupResult(V, conflict_f, &result);
    acc_out->is_hit = GetGemPortCpuLookupResult(V, lookupResultValid_f, &result);

    /*acording lookup result build prepare information*/
    if (!GetGemPortCpuLookupResult(V, conflict_f, &result))
    {
        acc_out->key_index = GetGemPortCpuLookupResult(V, resultIndex_f, &result);
    }

#if 0
    DRV_DBG_OUT("=============================\n");
    DRV_DBG_OUT("Lookup keyinex:%d\n", pre_info->key_index);
    DRV_DBG_OUT("conflict:%d\n", pre_info->conflict);
    DRV_DBG_OUT("valid:%d\n", pre_info->valid);

#endif

    return ret;
}


/* for host0 acc*/
int32
drv_usw_acc_host0(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    uint8   cam_num = 0;
    int32   ret= 0;
    FibHashKeyCpuReq_m fib_req;
    FibHashKeyCpuResult_m fib_result;
    uint32  mem_db_tbl_id = 0;
    uint32  mem_db_index  = 0;
    uint32  entry_size = 0;
    uint8  sleep_en = (acc_in->type == DRV_ACC_TYPE_FLUSH || acc_in->op_type == DRV_ACC_TYPE_DUMP);

   FIB_ACC_LOCK(lchip);
    sal_memset(&fib_req, 0, sizeof(FibHashKeyCpuReq_m));

    DRV_IF_ERROR_RETURN_WITH_UNLOCK(drv_usw_acc_host0_prepare(lchip, acc_in, (uint32*)&fib_req),
        p_drv_master[lchip]->fib_acc_mutex);
    DRV_IF_ERROR_RETURN_WITH_UNLOCK(drv_usw_acc_host0_process(lchip, (uint32*)&fib_req, (uint32*)&fib_result,sleep_en, 0),
        p_drv_master[lchip]->fib_acc_mutex);
    FIB_ACC_UNLOCK(lchip);
    DRV_IF_ERROR_RETURN(drv_usw_acc_host0_result(lchip, acc_in, (uint32*)&fib_result, acc_out));

    /***MEM_DB BACKUP STORE***
    D2:Will get fibhost0 and fdb tbl,but only want fibhost0/fdb tbl.
    TM:Drv-io will get fibhost0 tbl  too.Do not backup here.
    */
    if (DRV_IS_DUET2(lchip))
    {
        if (acc_in->type == DRV_ACC_TYPE_ADD)
        {
            mem_db_tbl_id = acc_in->tbl_id;
            if (acc_in->op_type == DRV_ACC_OP_BY_INDEX)
            {
                mem_db_index  = acc_in->index;
            }

            if (acc_in->op_type == DRV_ACC_OP_BY_KEY)
            {
                mem_db_index  = acc_out->key_index;
            }
            cam_num = g_drv_app_master[lchip].hash_info[hash_module].cam_num;
            entry_size = TABLE_ENTRY_SIZE(lchip, mem_db_tbl_id);
            if (DRV_ACC_HASH_MODULE_FIB_HOST0 == hash_module && mem_db_index < cam_num)
            {
                DRV_IF_ERROR_RETURN(drv_sdb_store(lchip, DsFibHost0HashCam_t, mem_db_index, acc_in->data, entry_size, 0));
            }
            else if (DRV_ACC_HASH_MODULE_FIB_HOST0 == hash_module)
            {
                DRV_IF_ERROR_RETURN(drv_sdb_store(lchip, mem_db_tbl_id, mem_db_index - cam_num, acc_in->data, entry_size, 0));
            }
        }
    }

    return ret;
}

/* for host1/xcoam/flow/userid acc*/
int32
drv_usw_acc_hash(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
   drv_cpu_acc_prepare_info_t pre_info;
    uint32 write_data[12] = { 0 };

    sal_memset(&pre_info, 0, sizeof(drv_cpu_acc_prepare_info_t));
    pre_info.data = write_data;

    CPU_ACC_LOCK(lchip);

    pre_info.cam_step = g_drv_app_master[lchip].hash_info[hash_module].cam_step;
    pre_info.cam_num = g_drv_app_master[lchip].hash_info[hash_module].cam_num;
    pre_info.cam_table = g_drv_app_master[lchip].hash_info[hash_module].cam_tbl_id;
    pre_info.hash_type = hash_module;
    pre_info.tbl_id = acc_in->tbl_id;
    pre_info.key_index = acc_in->index;
    pre_info.oper_bmp = acc_in->oper_bmp;

   if (acc_in->op_type != DRV_ACC_OP_BY_INDEX)
   { /*By Key */
        DRV_IF_ERROR_RETURN_WITH_UNLOCK(p_drv_master[lchip]->acc_pre_cb[hash_module](lchip, acc_in, &pre_info), p_drv_master[lchip]->cpu_acc_mutex);
   }
   else
   {
     if (((pre_info.key_index < pre_info.cam_num) && (hash_module != DRV_ACC_HASH_MODULE_QUEUE_MAP_HASH)
        && hash_module != DRV_ACC_HASH_MODULE_DOT1AE)
        || ((hash_module == DRV_ACC_HASH_MODULE_DOT1AE) && acc_in->value)
          || ((pre_info.key_index >= TABLE_MAX_INDEX(lchip, DsQueueMapHashKey_t))
              && (hash_module == DRV_ACC_HASH_MODULE_QUEUE_MAP_HASH)))
      {
         pre_info.is_cam = 1;
      }
      if ((hash_module == DRV_ACC_HASH_MODULE_DOT1AE) && acc_in->value)
      {
         pre_info.cam_table = ((acc_in->dir) ? DsXSecTxHashCam_t : DsXSecRxHashCam_t);
      }
   }

   if(acc_in->type == DRV_ACC_TYPE_ADD)
   {
       pre_info.data = acc_in->data;
   }
   else  if(acc_in->type == DRV_ACC_TYPE_DEL)
    {
         sal_memset((uint8*)pre_info.data, 0, 48);
    }
    else if(acc_in->type == DRV_ACC_TYPE_ALLOC)
    {
         sal_memset((uint8*)pre_info.data, 0xFF, 48);
    }

    pre_info.is_read = acc_in->type == DRV_ACC_TYPE_LOOKUP;
    if ((!pre_info.conflict) && !((acc_in->type == DRV_ACC_TYPE_ALLOC) && pre_info.valid))
    {
        /* prepare conflict, should do nothing */
        DRV_IF_ERROR_RETURN_WITH_UNLOCK(drv_usw_acc_hash_process(lchip, &pre_info), p_drv_master[lchip]->cpu_acc_mutex);
    }

    CPU_ACC_UNLOCK(lchip);
    drv_usw_acc_hash_result(lchip, acc_in, &pre_info, acc_out);

    return DRV_E_NONE;
}


/*for mac limit process*/
int32
drv_usw_acc_mac_limit(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    int32 ret = 0;
    FibHashKeyCpuReq_m fib_req;
    FibHashKeyCpuResult_m fib_result;

    sal_memset(&fib_req, 0, sizeof(FibHashKeyCpuReq_m));
   FIB_ACC_LOCK(lchip);

   if(acc_in->type == DRV_ACC_TYPE_ADD)
    {
       ret = _drv_usw_acc_prepare_write_mac_limit(lchip, acc_in, (uint32*)&fib_req);
       ret = ret?:drv_usw_acc_host0_process(lchip, (uint32*)&fib_req, (uint32*)&fib_result,0,0);
   }
   else
    {
       ret =  _drv_usw_acc_prepare_read_mac_limit(lchip, acc_in,  (uint32*)&fib_req);
       ret = ret?:drv_usw_acc_host0_process(lchip, (uint32*)&fib_req, (uint32*)&fib_result,0,0);
       acc_out->query_cnt    = GetFibHashKeyCpuResult(V, hashCpuLuIndex_f, &fib_result);
       acc_out->is_full      = GetFibHashKeyCpuResult(V, hashCpuKeyHit_f,&fib_result);
    }

    FIB_ACC_UNLOCK(lchip);
    return ret;
}

/*only for ipfix acc*/
int32
drv_usw_acc_ipfix(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    int32   ret = 0;
    IpfixHashAdCpuReq_m ipfix_req;
    IpfixHashAdCpuResult_m ipfix_result;

    sal_memset(&ipfix_req, 0, sizeof(IpfixHashAdCpuReq_m));

    IPFIX_ACC_LOCK(lchip);
     ret = drv_usw_acc_ipfix_prepare(lchip, acc_in, (uint32*)&ipfix_req);
     ret = ret?:drv_usw_acc_ipfix_process(lchip, acc_in->dir, (uint32*)&ipfix_req, (uint32*)&ipfix_result);
    IPFIX_ACC_UNLOCK(lchip);
     ret = ret?:drv_usw_acc_ipfix_result(lchip, acc_in, (uint32*)&ipfix_result, acc_out);
    return ret;
}


/* for cid acc:  only support add by index and lookup  by key*/
int32
drv_usw_acc_cid(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    int32   ret = 0;


    CID_ACC_LOCK(lchip);

    if (acc_in->type ==DRV_ACC_TYPE_ADD && acc_in->op_type == DRV_ACC_OP_BY_INDEX )
    {
      DsCategoryIdPairHashLeftKey_m cid_data;
      uint8  entry_size_in_word = TABLE_ENTRY_SIZE(lchip, DsCategoryIdPairHashLeftKey_t)>>3;
    /*re-coding hash data*/
#if (SDB_DISABLE != SDB_MODE && SDK_WORK_PLATFORM == 0)
        if (DRV_READ_MEM_FROM_SER(acc_in->tbl_id))
        {
            sal_memcpy(&cid_data, (uint8*)drv_sdb_read(lchip, acc_in->tbl_id, acc_in->index, TABLE_ENTRY_SIZE(lchip, acc_in->tbl_id), acc_in->oper_bmp), TABLE_ENTRY_SIZE(lchip, acc_in->tbl_id));
        }
        else
#endif
        DRV_APP_TBL_IOR(lchip,acc_in->tbl_id,acc_in->index,&cid_data,DRV_ACC_PP_EN);
       if (!acc_in->offset)
       {
           sal_memcpy(&cid_data, (uint32*)acc_in->data, entry_size_in_word<<2);
       }
       else
       {
           sal_memcpy(((uint32*)&cid_data+entry_size_in_word), (uint32*)acc_in->data, entry_size_in_word<<2);
       }
       DRV_APP_TBL_IOW(lchip,acc_in->tbl_id, acc_in->index,&cid_data,acc_in->oper_bmp);
    }
   else  if (acc_in->type ==DRV_ACC_TYPE_LOOKUP && acc_in->op_type == DRV_ACC_OP_BY_KEY )
    {
        ret = drv_usw_acc_cid_lookup(lchip, acc_in, acc_out);
    }

    CID_ACC_UNLOCK(lchip);
    return ret;
}


STATIC INLINE int32
_drv_usw_acc_mpls_lookup(uint8 lchip, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    int32   ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    MplsCpuLookupReq_m req;
    MplsCpuLookupResult_m result;
#if(SDK_WORK_PLATFORM == 0)
    uint32 req_val = 0;
#endif
    sal_memset(&req, 0, sizeof(req));

    SetMplsCpuLookupReq(V, mplsCpuLookupReqValid_f, &req, 1);
    SetMplsCpuLookupReq(A, mplsData_f, &req, acc_in->data);
    DRV_APP_REG_IOW(lchip,MplsCpuLookupReq_t,&req,DRV_ACC_PP_EN);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }

#if(SDK_WORK_PLATFORM == 0)
         DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_MPLS)), &req_val));
         not_done = (req_val & (1 << DRV_CONST(DRV_ACCREQ_BITOFFSET_MPLS)));
#else
         DRV_APP_REG_IOR(lchip,MplsCpuLookupReq_t,&req,DRV_ACC_PP_EN);
         not_done = GetMplsCpuLookupReq(V, mplsCpuLookupReqValid_f, &req);
#endif

        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,MplsCpuLookupResult_t,&result,DRV_ACC_PP_EN);
    acc_out->is_conflict = GetMplsCpuLookupResult(V, mplsConflict_f, &result);
    acc_out->is_hit = GetMplsCpuLookupResult(V, mplsLookupResultValid_f, &result);

    /*acording lookup result build prepare information*/
    if (!GetMplsCpuLookupResult(V, mplsConflict_f, &result))
    {
        acc_out->key_index = GetMplsCpuLookupResult(V, mplsResultIndex_f, &result);
    }

 #if 0
    DRV_DBG_OUT("=============================\n");
    DRV_DBG_OUT("Lookup keyinex:%d\n", pre_info->key_index);
    DRV_DBG_OUT("conflict:%d\n", pre_info->conflict);
    DRV_DBG_OUT("valid:%d\n", pre_info->valid);

 #endif

    return ret;
}

/* for mpls acc*/
int32
drv_usw_acc_mpls(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    int32   ret = 0;
    uint8  cam_num = g_drv_app_master[lchip].hash_info[DRV_ACC_HASH_MODULE_MPLS_HASH].cam_num;
    uint32 cam_tbl = g_drv_app_master[lchip].hash_info[DRV_ACC_HASH_MODULE_MPLS_HASH].cam_tbl_id;
    uint32 write_data[12] = { 0 };

    MPLS_ACC_LOCK(lchip);
    acc_out->key_index = acc_in->index;
    acc_out->is_conflict = 0;
    acc_out->is_hit = 0;
    if (acc_in->op_type != DRV_ACC_OP_BY_INDEX)
    {
      ret = _drv_usw_acc_mpls_lookup(lchip, acc_in, acc_out);
    }
    if ((!acc_out->is_conflict) && !((acc_in->type == DRV_ACC_TYPE_ALLOC) && acc_out->is_hit))
    {
        uint32 tbl_id = (acc_out->key_index < cam_num)?cam_tbl:acc_in->tbl_id;
        uint32 index = (acc_out->key_index < cam_num)?acc_out->key_index :(acc_out->key_index -cam_num);
#if (SDB_DISABLE != SDB_MODE && SDK_WORK_PLATFORM == 0)
        uint32 entry_offset = (acc_out->key_index < cam_num)? TABLE_ENTRY_SIZE(lchip, tbl_id) : DYNAMIC_TABLE_UNIT_SIZE(lchip, tbl_id);
        if(acc_in->type == DRV_ACC_TYPE_LOOKUP)
        {
            if (DRV_READ_MEM_FROM_SER(tbl_id))
            {
              sal_memcpy(acc_out->data, (uint8*)drv_sdb_read(lchip, tbl_id, index, entry_offset, acc_in->oper_bmp), TABLE_ENTRY_SIZE(lchip, tbl_id));
            }
            else
            {
                DRV_APP_TBL_IOR(lchip, tbl_id, index, acc_out->data, acc_in->oper_bmp);
            }
        }
        else
        {/*alloc/add/remove */
            DRV_APP_TBL_IOW(lchip,tbl_id,index,((acc_in->type == DRV_ACC_TYPE_ADD) ? acc_in->data:&write_data[0]),acc_in->oper_bmp);
        }
#else
        if(acc_in->type == DRV_ACC_TYPE_LOOKUP)
        {
          DRV_APP_TBL_IOR(lchip,tbl_id,index,acc_out->data,DRV_ACC_PP_EN);
        }
        else
        {/*alloc/add/remove */
           DRV_APP_TBL_IOW(lchip,tbl_id,index,((acc_in->type == DRV_ACC_TYPE_ADD) ? acc_in->data:&write_data[0]),acc_in->oper_bmp);
        }
#endif
    }
    MPLS_ACC_UNLOCK(lchip);
    return ret ;

}

/* for  gemport acc*/
int32
drv_usw_acc_gemport(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out)
{
    int32   ret = 0;
    uint8  cam_num = g_drv_app_master[lchip].hash_info[DRV_ACC_HASH_MODULE_GEMPORT_HASH].cam_num;
    uint32 cam_tbl = g_drv_app_master[lchip].hash_info[DRV_ACC_HASH_MODULE_GEMPORT_HASH].cam_tbl_id;
    uint32 write_data[12] = { 0 };

    GEMPORT_ACC_LOCK(lchip);
    acc_out->key_index = acc_in->index;
    acc_out->is_conflict = 0;
    acc_out->is_hit = 0;

    if (acc_in->op_type != DRV_ACC_OP_BY_INDEX)
    {
        ret = _drv_usw_acc_gemport_lookup(lchip, acc_in, acc_out);
    }

    if ((!acc_out->is_conflict) && !((acc_in->type == DRV_ACC_TYPE_ALLOC) && acc_out->is_hit))
    {
        uint32 tbl_id = (acc_out->key_index < cam_num)?cam_tbl:acc_in->tbl_id;
        uint32 index = (acc_out->key_index < cam_num)?acc_out->key_index :(acc_out->key_index -cam_num);
#if (SDB_DISABLE != SDB_MODE && SDK_WORK_PLATFORM == 0)
        uint32 entry_offset = (acc_out->key_index < cam_num)? TABLE_ENTRY_SIZE(lchip, tbl_id): DYNAMIC_TABLE_UNIT_SIZE(lchip, tbl_id);
       if(acc_in->type == DRV_ACC_TYPE_LOOKUP)
       {
             if (DRV_READ_MEM_FROM_SER(tbl_id))
             {
                 sal_memcpy(acc_out->data, (uint8*)drv_sdb_read(lchip, tbl_id, index, entry_offset, acc_in->oper_bmp), TABLE_ENTRY_SIZE(lchip, tbl_id));
             }
             else
             {
                 DRV_APP_TBL_IOR(lchip, tbl_id, index, acc_out->data, acc_in->oper_bmp);
             }
       }
       else
       {/*alloc/add/remove */
            DRV_APP_TBL_IOW(lchip,tbl_id,index,((acc_in->type == DRV_ACC_TYPE_ADD) ? acc_in->data:&write_data[0]),DRV_ACC_PP_EN);
       }
#else
        if(acc_in->type == DRV_ACC_TYPE_LOOKUP)
       {
             DRV_APP_TBL_IOR(lchip,tbl_id,index,acc_out->data,DRV_ACC_PP_EN);
       }
       else
       {/*alloc/add/remove */
            DRV_APP_TBL_IOW(lchip,tbl_id,index,((acc_in->type == DRV_ACC_TYPE_ADD) ? acc_in->data:&write_data[0]),DRV_ACC_PP_EN);
       }
#endif
    }
    GEMPORT_ACC_UNLOCK(lchip);
    return ret;
}
int32 drv_acc_fdb_calc_index(uint8 lchip, void* in, void* out)
{
    if (DRV_IS_DUET2(lchip))
    {
#ifdef DUET2
        return _drv_usw_host0_calc_fdb_index(lchip, in, out);       
#endif
    }
#ifdef TSINGMA
    else if(DRV_IS_TSINGMA(lchip))
    {
        return _drv_usw_host0_calc_fdb_index_tsingma(lchip, in, out);
    }
#endif
#if defined(TSINGMA_MX) || defined(TSINGMA_GX)
        else if((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
    {
        return _drv_usw_host0_calc_fdb_index_tsingma_mx(lchip, in, out);
    }
#endif
#ifdef ARCTIC
    else if(DRV_IS_AT(lchip))
    {
        return _drv_usw_host0_calc_fdb_index_arctic(lchip, in, out);
    }
#endif

    return DRV_E_NONE;

}

/* FDB don't need  to strore SDB, because it can recovery FDB by cb in chipreset mode  */

int32
drv_usw_acc_ipl2mc(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* out)
{
    int32 ret = 0;
    FibHashKeyCpuReq_m fib_req;
    FibHashKeyCpuResult_m fib_result;
   uint8  by_key = (acc_in->op_type == DRV_ACC_OP_BY_KEY);

   sal_memset(&fib_req, 0, sizeof(FibHashKeyCpuReq_m));

   FIB_ACC_LOCK(lchip);

    if(by_key && acc_in->type == DRV_ACC_TYPE_ADD
        && DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_OVERWRITE_EN))
    {
           drv_cpu_acc_prepare_info_t pre_info;

           sal_memset(&pre_info, 0, sizeof(drv_cpu_acc_prepare_info_t));
           if(acc_in->type == DRV_ACC_TYPE_LOOKUP)
              pre_info.data = out->data;
           else
               pre_info.data = acc_in->data;
           pre_info.cam_step = g_drv_app_master[lchip].hash_info[hash_module].cam_step;
           pre_info.cam_num = g_drv_app_master[lchip].hash_info[hash_module].cam_num;
           pre_info.cam_table = g_drv_app_master[lchip].hash_info[hash_module].cam_tbl_id;
           pre_info.hash_type = hash_module;
           pre_info.tbl_id = acc_in->tbl_id;
           pre_info.is_cam = acc_in->index < pre_info.cam_num;
           pre_info.key_index = acc_in->index;
           pre_info.is_read = acc_in->type == DRV_ACC_TYPE_LOOKUP;
           ret = drv_usw_acc_hash_process(lchip, &pre_info);
           out->is_hit  =1;
           out->key_index = acc_in->index;
           FIB_ACC_UNLOCK(lchip);
           return ret;
    }

    if(by_key && ((acc_in->type == DRV_ACC_TYPE_ADD &&!DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_OVERWRITE_EN))
             || (acc_in->type == DRV_ACC_TYPE_LOOKUP) ))
    {
         uint16 fid = 0;
         uint32 ad_idx = 0;
         uint16 pointer = 0;

         if(acc_in->tbl_id == DsFibHost0MacIpv4McastHashKey_t)
         {
              uint32 ipv4[2] = {0};
              DsFibHost0MacIpv4McastHashKey_m* p_hash_key = (DsFibHost0MacIpv4McastHashKey_m*)acc_in->data;

              ipv4[0] = GetDsFibHost0MacIpv4McastHashKey(V, ipDa_f, p_hash_key);
              fid = DRV_FROM_AT(lchip) ?  GetDsFibHost0MacIpv4McastHashKey(V, vsiId_f, p_hash_key) : GetDsFibHost0MacIpv4McastHashKey(V, vrfId_f, p_hash_key);
              ad_idx = GetDsFibHost0MacIpv4McastHashKey(V, dsAdIndex_f, p_hash_key);
              pointer = GetDsFibHost0MacIpv4McastHashKey(V, pointer_f, p_hash_key);

              SetFibHashKeyCpuReq(A, cpuKeyMac_f, &fib_req, ipv4);
              SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, &fib_req, fid);
              SetFibHashKeyCpuReq(V, cpuKeyDsAdIndex_f, &fib_req, ad_idx);
              SetFibHashKeyCpuReq(V, cpuKeyIndex_f, &fib_req, pointer);
              SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, &fib_req, 0);
         }
         else
         {
              ipv6_addr_t ipv6;
              ipv6_addr_t ipv6_2 ;
              DsFibHost0MacIpv6McastHashKey_m* p_hash_key = (DsFibHost0MacIpv6McastHashKey_m*)acc_in->data;

              GetDsFibHost0MacIpv6McastHashKey(A, ipDa_f, p_hash_key,&ipv6);
              fid = GetDsFibHost0MacIpv6McastHashKey(V, vsiId_f, p_hash_key);
              ad_idx = GetDsFibHost0MacIpv6McastHashKey(V, dsAdIndex_f, p_hash_key);
              pointer = GetDsFibHost0MacIpv6McastHashKey(V, pointer_f, p_hash_key);

              ipv6_2[0] =((ipv6[2] & 0xFFFF)<<16) | ipv6[1] >>16;
              ipv6_2[1] =((ipv6[3] & 0xFFFF)<<16) | ipv6[2] >>16;
              ipv6_2[2] = ipv6[3] >> 16;
              ipv6_2[3] = 0;
              SetFibHashKeyCpuReq(A, cpuKeyMac_f, &fib_req, &ipv6);//ipDa(47,0)
              SetFibHashKeyCpuReq(A, ipv6DaHighBits_f, &fib_req, &ipv6_2);//ipDa(119,48)
              SetFibHashKeyCpuReq(V, cpuKeyVrfId_f, &fib_req, fid);
              SetFibHashKeyCpuReq(V, cpuKeyDsAdIndex_f, &fib_req, ad_idx);
              SetFibHashKeyCpuReq(V, cpuKeyIndex_f, &fib_req, pointer);
              SetFibHashKeyCpuReq(V, cpuKeyPortDelMode_f, &fib_req, 1);

          }
          SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, &fib_req, 1);
          SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, &fib_req, (acc_in->type == DRV_ACC_TYPE_LOOKUP)?9:7);
    }
    else  if(!by_key && acc_in->type == DRV_ACC_TYPE_DEL)
    {
       SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, &fib_req, 1);
       SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f,  &fib_req,2);
       SetFibHashKeyCpuReq(V, cpuKeyIndex_f, &fib_req, acc_in->index);
    }
    else  if(!by_key && acc_in->type == DRV_ACC_TYPE_LOOKUP)
    {
       SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, &fib_req, 1);
       SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f,  &fib_req,2);
       SetFibHashKeyCpuReq(V, cpuKeyMac_f, &fib_req, acc_in->index);
       SetFibHashKeyCpuReq(V, hashKeyCpuReqType_f, &fib_req, (acc_in->tbl_id == DsFibHost0MacIpv4McastHashKey_t)?8:10);

    }
    else
    {
        FIB_ACC_UNLOCK(lchip);
        return DRV_E_INVAILD_TYPE;
    }
   ret = drv_usw_acc_host0_process(lchip, (uint32*)&fib_req, (uint32*)&fib_result,0,0);
   if(acc_in->type == DRV_ACC_TYPE_DEL && (acc_in->tbl_id == DsFibHost0MacIpv6McastHashKey_t))
   {
       SetFibHashKeyCpuReq(V, hashKeyCpuReqValid_f, &fib_req, 1);
       SetFibHashKeyCpuReq(V, cpuKeyIndex_f, &fib_req, acc_in->index+1);
      ret = ret ? ret : drv_usw_acc_host0_process(lchip, (uint32*)&fib_req, (uint32*)&fib_result,0, 0);
   }
   if(!by_key && (acc_in->type == DRV_ACC_TYPE_LOOKUP))
    {
       uint8  read_data[24];
       uint8  write_data[24];
       uint8  loop = 0;
       GetFibHashKeyCpuResult(A, readData_f, &fib_result, read_data);
       if(DRV_FROM_AT(lchip))
       {
           sal_memcpy(&write_data[0], &read_data[0], 11);
           sal_memcpy(&write_data[12], &read_data[11], 11);
       }
       else
       {
           sal_memcpy(&write_data[0], &read_data[0], 10);
           write_data[10] = read_data[10] & 0x7F;
           write_data[11] = 0;
           for (loop = 0; loop < 11 ; loop++ )
           {
               write_data[12 + loop] = ((read_data[11 + loop] & 0x7F) << 1) |  (read_data[10 + loop] >> 7) ;
           }
       }
       sal_memcpy(&out->data[0], &write_data[0],24);
    }
   else
   {
      ret = ret ? ret : p_drv_master[lchip]->fdb_rst_cb[acc_in->type][by_key](lchip, acc_in, (uint32*)&fib_result, out);
   }

   FIB_ACC_UNLOCK(lchip);
   return ret;
}


int32
drv_usw_acc_fdb_cb(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* out)
{
    int32 ret = 0;
    FibHashKeyCpuReq_m fib_req;
    FibHashKeyCpuResult_m fib_result;
    uint8  by_key = (acc_in->op_type == DRV_ACC_OP_BY_KEY);
    uint8  sleep_en = (acc_in->type == DRV_ACC_TYPE_FLUSH || acc_in->type == DRV_ACC_TYPE_FLUSH_FLEX||
                          acc_in->type == DRV_ACC_TYPE_DUMP || acc_in->type == DRV_ACC_TYPE_DUMP_FLEX);

   FIB_ACC_LOCK(lchip);

   if (p_drv_master[lchip]->eunit_lock_en && p_drv_master[lchip]->eunit_lock_cb)
   {
       p_drv_master[lchip]->eunit_lock_cb(lchip, DRV_EUNIT_LOCK_FIBACC, 1);
   }

   sal_memset(&fib_req, 0, sizeof(FibHashKeyCpuReq_m));
    if (acc_in->type == DRV_ACC_TYPE_DUMP_FLEX)
   {
        acc_in->oper_bmp = DRV_ACC_PP_EN;
   }
   ret =  p_drv_master[lchip]->fdb_pre_cb[acc_in->type][by_key](lchip,acc_in, (uint32*)&fib_req);
   ret = ret ? ret : drv_usw_acc_host0_process(lchip, (uint32*)&fib_req, (uint32*)&fib_result,sleep_en,acc_in->oper_bmp);
   ret = ret ? ret : p_drv_master[lchip]->fdb_rst_cb[acc_in->type][by_key](lchip, acc_in, (uint32*)&fib_result, out);

   if (p_drv_master[lchip]->eunit_lock_en && p_drv_master[lchip]->eunit_lock_cb)
   {
       p_drv_master[lchip]->eunit_lock_cb(lchip, DRV_EUNIT_LOCK_FIBACC, 0);
   }

   FIB_ACC_UNLOCK(lchip);


   return ret;
}
extern uint8 drv_vchip_pp_num[DRV_MAX_CHIP_NUM];
/*drv layer acc interface*/
int32
drv_usw_acc_init(uint8 lchip)
{
        uint8 loop = 0;
        uint32 tbl_id = 0;
        uint8 cam_step = 0;   

#if defined(EMULATION_ENV) && !defined(EMULATOR_ENV)
{
    uint8 first_pp_id = 0;
    extern uint32 g_drv_oper_bmp;
    for (loop = 0; loop < PP_NUM_PER_CORE; loop++)
    {
        if (DRV_IS_BIT_SET(g_drv_oper_bmp >> 2, loop))
        {
            first_pp_id = loop;
            break;
        }
    }
    for (loop = 0; loop < PP_NUM_PER_CORE; loop++)
    {
        g_drv_lchip_2_pp[loop] = DRV_IS_BIT_SET(g_drv_oper_bmp >> 2, loop) ? loop : first_pp_id;
    }
}
#endif

      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_FDB] = drv_usw_acc_fdb_cb;
      if (DRV_IS_DUET2(lchip))
      {
          p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_FIB_HOST0] = drv_usw_acc_host0;
      }
      else
      {
          p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_FIB_HOST0] = drv_usw_acc_hash;
      }
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_IPL2MC] = drv_usw_acc_ipl2mc;


      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_FIB_HOST1] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_EGRESS_XC] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_FLOW] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_USERID] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_EGRESS_SCL] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_OAM] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_RMEP] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_QUEUE_MAP_HASH] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_MAC_LIMIT] = drv_usw_acc_mac_limit;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_IPFIX] = drv_usw_acc_ipfix;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_CID] = drv_usw_acc_cid;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_AGING] = drv_usw_acc_aging;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_MPLS_HASH] = drv_usw_acc_mpls;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_GEMPORT_HASH] = drv_usw_acc_gemport;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_DOT1AE] = drv_usw_acc_hash;
      p_drv_master[lchip]->drv_acc_cb[DRV_ACC_HASH_MODULE_X_FLOW] = drv_usw_acc_hash;

      p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_EGRESS_XC] = _drv_usw_acc_prepare_xcoam_by_key;
      if (DRV_DUET2 == drv_get_chip_type(lchip))
      {
          p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FLOW] =_drv_usw_acc_prepare_flow_by_key;
          p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FIB_HOST1] =_drv_usw_acc_prepare_host1_by_key;
          p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FIB_HOST0] =_drv_usw_acc_prepare_host1_by_key;
      }
      else if (DRV_TSINGMA == drv_get_chip_type(lchip))
      {
         p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FLOW] =_drv_usw_acc_prepare_fib_hash_by_key;
         p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FIB_HOST1] =_drv_usw_acc_prepare_fib_hash_by_key;
         p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FIB_HOST0] =_drv_usw_acc_prepare_fib_hash_by_key;
      }
      p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_OAM] =_drv_usw_acc_prepare_oam_by_key;
      p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_RMEP] =_drv_usw_acc_prepare_rmep_by_key;
      p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_QUEUE_MAP_HASH] =_drv_usw_acc_prepare_queue_map_by_key;
      p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_DOT1AE] =_drv_usw_acc_prepare_dot1ae_by_key;

     for(loop = 0; loop < DRV_ACC_HASH_MODULE_NUM; loop++)
     {
        drv_usw_get_cam_info(lchip, loop, &tbl_id, &g_drv_app_master[lchip].hash_info[loop].cam_num);
        cam_step = (loop == DRV_ACC_HASH_MODULE_RMEP)? 4 :
                    (loop == DRV_ACC_HASH_MODULE_FIB_HOST0) ?
                        (TABLE_ENTRY_SIZE(lchip, tbl_id) / DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE))
                        : (TABLE_ENTRY_SIZE(lchip, tbl_id) / SINGLE_KEY_BYTE);
        cam_step = (loop == DRV_ACC_HASH_MODULE_QUEUE_MAP_HASH)? 1 : cam_step;
        g_drv_app_master[lchip].hash_info[loop].cam_tbl_id = tbl_id;
        g_drv_app_master[lchip].hash_info[loop].cam_step = cam_step;
     }
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_ADD][0] = _drv_usw_acc_prepare_write_mac_by_idx;     
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_ADD][1] = _drv_usw_acc_prepare_write_mac_by_key;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DEL][0] = _drv_usw_acc_prepare_del_mac_by_idx;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DEL][1] = _drv_usw_acc_prepare_del_mac_by_key;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_LOOKUP][0] = _drv_usw_acc_prepare_lkp_fib0_by_idx;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_LOOKUP][1] = _drv_usw_acc_prepare_lkp_mac_by_key;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DUMP][0] = _drv_usw_acc_prepare_dump;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DUMP][1] = _drv_usw_acc_prepare_dump;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_FLUSH][0] = _drv_usw_acc_prepare_flush;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_FLUSH][1] = _drv_usw_acc_prepare_flush;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_ADD][1] = _drv_usw_acc_result_write_mac_by_key;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DEL][1] = _drv_usw_acc_result_del_mac_by_key;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_LOOKUP][1] = _drv_usw_acc_result_lkp_mac_by_key;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DUMP][0] = _drv_usw_acc_result_dump_mac;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DUMP][1] = _drv_usw_acc_result_dump_mac;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DUMP_FLEX][0] = _drv_usw_acc_result_flex;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DUMP_FLEX][1] = _drv_usw_acc_result_flex;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_FLUSH_FLEX][0] = _drv_usw_acc_result_flex;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_FLUSH_FLEX][1] = _drv_usw_acc_result_flex;
     p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_USERID] = _drv_usw_acc_prepare_userid_by_key;
     p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_EGRESS_SCL] =_drv_usw_acc_prepare_egress_scl_by_key;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DUMP_FLEX][0] = _drv_usw_acc_prepare_flex;//after TMM,dump all
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DUMP_FLEX][1] = _drv_usw_acc_prepare_flex;//after TMM,dump all
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_FLUSH_FLEX][0] = _drv_usw_acc_prepare_flex; //after TMM, flush all
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_FLUSH_FLEX][1] = _drv_usw_acc_prepare_flex; //after TMM, flush all
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_ALLOC][0] = _drv_usw_acc_prepare_null;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_ALLOC][1] = _drv_usw_acc_prepare_null;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_UPDATE][0] = _drv_usw_acc_prepare_null;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_UPDATE][1] = _drv_usw_acc_prepare_null;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_FLUSH_CACHE][0] = _drv_usw_acc_prepare_flush_cache;
     p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_FLUSH_CACHE][1] = _drv_usw_acc_prepare_flush_cache;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_ADD][0] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DEL][0] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_LOOKUP][0] = _drv_usw_acc_result_lkp_fib0_by_idx;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_FLUSH][0] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_FLUSH][1] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_ALLOC][0] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_ALLOC][1] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_UPDATE][0] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_UPDATE][1] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_FLUSH_CACHE][0] = _drv_usw_acc_result_null;
     p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_FLUSH_CACHE][1] = _drv_usw_acc_result_null;
#ifdef TSINGMA_MX
    if (DRV_IS_TMM(lchip))
    {
        drv_tmm_app_api_init(lchip);
    }
#endif
     if (DRV_FROM_AT(lchip))/*AT_TODO*/
     {
#ifdef ARCTIC
         drv_at_app_api_init(lchip);
#endif
         for (loop = lchip + 1; loop < drv_vchip_get_pp_num(lchip) + lchip; loop++)
         {
            sal_memcpy(&g_drv_app_master[loop], &g_drv_app_master[lchip], sizeof(drv_acc_master_t));
         }
#if (SDK_WORK_PLATFORM == 1)
        if (g_drv_vchip_mode)
        {
            for (loop = lchip + drv_vchip_get_pp_num(lchip); loop < lchip + drv_vchip_get_pp_num(lchip)*2; loop++)
            {
                sal_memcpy(&g_drv_app_master[loop], &g_drv_app_master[lchip], sizeof(drv_acc_master_t));
            }
        }
#endif
     }

     return DRV_E_NONE;
}
int32
drv_usw_ftm_get_entry_size(uint8 lchip, uint32 table_id, uint32* entry_size)
{
    *entry_size = TABLE_ENTRY_SIZE(lchip, table_id);

    return DRV_E_NONE;
}

